參數(shù)資料
型號: NAND04GR4B2CN1F
廠商: NUMONYX
元件分類: PROM
英文描述: 256M X 16 FLASH 1.8V PROM, 35 ns, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù): 17/57頁
文件大?。?/td> 887K
代理商: NAND04GR4B2CN1F
NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
24/57
Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back Program operation bit error due to
charge loss cannot be detected. For this reason it
is recommended to limit the number of Copy Back
Program operations on the same data and or to
improve the performance of the ECC.
The Copy Back Program operation requires four
steps:
1.
The first step reads the source page. The
operation copies all 1056 Words/ 2112 Bytes
from the page into the Data Buffer. It requires:
one bus write cycle to setup the command
4 bus write cycles to input the source page
address
one bus write cycle to issue the confirm
command code
2.
When the device returns to the ready state
(Ready/Busy High), the next bus write cycle of
the command is given with the 4 bus cycles to
input the target page address. Refer to Table
11. for the addresses that must be the same
for the Source and Target pages.
3.
Then the confirm command is issued to start
the P/E/R Controller.
To see the Data Input cycle for modifying the
source page and an example of the Copy Back
Program operation refer to Figure 13. .
A data input cycle to modify a portion or a multiple
distant portion of the source page, is shown in Fig-
Table 11. Copy Back Program x8 Addresses
Note: 1. DD = Dual Die
Table 12. Copy Back Program x16 Addresses
Note: 1. DD = Dual Die
Density
Same Address for Source and
Target Pages
1 Gbit
no constraint
2 Gbit
no constraint
2 Gbit DD(1)
A28
4 Gbit
no constraint
Density
Same Address for Source and
Target Pages
1 Gbit
no constraint
2 Gbit
A28
2 Gbit DD(1)
A27
4 Gbit
no constrain
相關PDF資料
PDF描述
NAND08GW3B2CZL1F 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
NAND128W3A2BV6E 16M X 8 FLASH 3V PROM, 12000 ns, PDSO48
NAND512R3A2CV6E 64M X 8 FLASH 1.8V PROM, 15000 ns, PDSO48
NAND128W4A2CZA6E 8M X 16 FLASH 3V PROM, 35 ns, PBGA55
NAND128R4A2BZA6E 8M X 16 FLASH 1.8V PROM, 35 ns, PBGA55
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