參數(shù)資料
型號(hào)： MTV112M
廠商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded CRT Monitor Controller Flash Version
中文描述： CRT顯示器8051嵌入式控制器Flash版本
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 160K
代理商： MTV112M
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 7 - 2001/05/18
HCNTH/HCNTL latch. The 11-bit output value is {2/H-Freq} / {1/OSC-Freq}, updated once per
VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC
is not present. The 14-bit Vcounter counts the time between 2 VSYNC pulses, but only 9 upper bits are
loaded into the VCNTH/VCNTL latch. The 9-bit output value is {1/V-Freq} / {512/OSC-Freq}, updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of the H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
shows the HCNT/VCNT value under the operations of 8MHz and 12MHz.
4.2.1 H-Freq Table
Output Value (11 bits)
H-Freq(KHZ)
8MHz OSC (hex / dec)
215h / 533
1FBh / 507
1DDh /477
1C2h / 450
1B2h / 434
1A5h / 421
190h / 400
14Dh / 333
140h / 320
118h / 280
10Ah / 266
0FAh / 250
0A0h / 160
12MHz OSC (hex / dec)
320h / 800
2F9h / 761
2CCh / 716
2A4h / 676
28Ch / 652
277h / 631
258h / 600
1F4h / 500
1E0h / 480
1A5h / 421
190h / 400
177h / 375
0F0h / 240
1
2
3
4
5
6
7
8
9
10
11
12
13
30
31.5
33.5
35.5
36.8
38
40
48
50
57
60
64
100
*1. The H-Freq output (HF10 - HF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.2.2 V-Freq Table
Output Value (9 bits)
V-Freq(Hz)
8MHz OSC (hex / dec)
115h / 277
104h / 260
104h / 260
103h / 259
102h / 258
0EAh / 234
0DEh / 222
0DEh / 222
0D9h /217
0D7h / 215
0D6h / 214
0B3h / 179
12MHz OSC (hex / dec)
1A0h / 416
187h / 391
186h / 390
184h / 388
183h / 387
15Fh / 351
14Eh / 334
14Eh / 334
145h / 325
143h / 323
142h / 322
10Dh / 269
1
2
3
4
5
6
7
8
9
10
11
12
56.25
59.94
60
60.32
60.53
66.67
70.069
70.08
72
72.378
72.7
87
*1. The V-Freq output (VF8 - VF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.3 H/V Presence Check
The Hpresent function checks the input HSYNC pulse. The Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse. The Vpre flag
is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. A control bit "PREFS" selects the
time base for these functions. The HPRchg interrupt is set when the Hpre value changes. The VPRchg
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