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參數(shù)資料
| 型號： | MTV112M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Flash Version |
| 中文描述： | CRT顯示器8051嵌入式控制器Flash版本 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | MTV112M |
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 6 - 2001/05/18
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
WDT
22h (r/w) DA2b7
23h (r/w) DA3b7
24h (r/w) DA4b7
25h (r/w) DA5b7
26h (r/w) DA6b7
27h (r/w) DA7b7
28h (r/w) DA8b7
29h (r/w) DA9b7
2Ah (r/w)
DA10b7 DA10b6 DA10b5 DA10b4 DA10b3 DA10b2 DA10b1 DA10b0
2Bh (r/w)
DA11b7 DA11b6 DA11b5 DA11b4 DA11b3 DA11b2 DA11b1 DA11b0
2Ch (r/w)
DA12b7 DA12b6 DA12b5 DA12b4 DA12b3 DA12b2 DA12b1 DA12b0
2Dh (r/w)
DA13b7 DA13b6 DA13b5 DA13b4 DA13b3 DA13b2 DA13b1 DA13b0
80h
WEN
WCLR
CLRDDC
DIV253
DA2b6
DA3b6
DA4b6
DA5b6
DA6b6
DA7b6
DA8b6
DA9b6
DA2b5
DA3b5
DA4b5
DA5b5
DA6b5
DA7b5
DA8b5
DA9b5
DA2b4
DA3b4
DA4b4
DA5b4
DA6b4
DA7b4
DA8b4
DA9b4
DA2b3
DA3b3
DA4b3
DA5b3
DA6b3
DA7b3
DA8b3
DA9b3
DA2b2
DA3b2
DA4b2
DA5b2
DA6b2
DA7b2
DA8b2
DA9b2
DA2b1
DA3b1
DA4b1
DA5b1
DA6b1
DA7b1
DA8b1
DA9b1
DA2b0
DA3b0
DA4b0
DA5b0
DA6b0
DA7b0
DA8b0
DA9b0
DACK
WDT2
WDT1
WDT0
DA0
(r/w) :
DA1
(r/w) :
DA2
(r/w) :
DA3
(r/w) :
DA4
(r/w) :
DA5
(r/w) :
DA6
(r/w) :
DA7
(r/w) :
DA8
(r/w) :
DA9
(r/w) :
DA10
(r/w) :
DA11
(r/w) :
DA12
(r/w) :
DA13
(r/w) :
WDT
(w) :
DIV253 = 1
= 0
DACK
The output pulse width control for DA0.
The output pulse width control for DA1.
The output pulse width control for DA2.
The output pulse width control for DA3.
The output pulse width control for DA4.
The output pulse width control for DA5.
The output pulse width control for DA6.
The output pulse width control for DA7.
The output pulse width control for DA8.
The output pulse width control for DA9.
The output pulse width control for DA10.
The output pulse width control for DA11.
The output pulse width control for DA12.
The output pulse width control for DA13.
Watchdog timer & special control bit.
→
The PWM DAC outputs frequency is (PWM clk frequency)/253.
→
The PWM DAC output frequency is Xtal frequency/256.
= 1
→
The PWM clk frequency is 2 x (X’tal frequency).
= 0
→
The PWM clk frequency is (X’tal frequency).
*1. All D/A converters are centered with value 80h after power-on.
4. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation, SYNC input
presence check, frequency counting, and polarity detection and control, as well as the protection of VBLANK
output while VSYNC speeds up to a high DDC communication clock rate. The present and frequency
function block treat any pulse less than one OSC period as noise.
4.1 Composite SYNC Separation
MTV112M continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity check,
frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original signal. The
delay depends on the OSC frequency and composite mix method.
4.2 H/V Frequency Counter
MTV112M can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 15-bit
Hcounter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the
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