參數(shù)資料
型號(hào)： MTV112M
廠商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded CRT Monitor Controller Flash Version
中文描述： CRT顯示器8051嵌入式控制器Flash版本
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 160K
代理商： MTV112M
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 13 - 2001/05/18
5.2 DDC2B Mode
MTV112M switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV112M enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the HSDA
and HSCL are directly bypassed to ISDA and ISCL pins. MTV112M will return to DDC1 mode if HSCL is
kept high for a 128 VSYNC clock period. However, it will lock in DDC2B mode if a valid IIC access has been
detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status. S/W may clear it by setting
CLRDDC. Control bits M128/M256 are used to block the EEPROM write operation from the host if the
address is over 128/256.
5.3 Master Mode IIC Function Block
The master mode IIC block is connected to the ISDA and ISCL pins. Its speed can be selected to 100kHz or
400kHz by s/w set IICF control bit while MORE=0, or to 50KHz,100KHz,200KHz or 400KHz by s/w set
(MCLK1,MCLK0) bits while MORE=1. The software program can access the external EEPROM through this
interface. Since the EDID/VDIF data and display information share the common EEPROM, precaution must
be taken to avoid bus conflict. In DDC1 mode, the IIC interface is controlled by MTV112M only. In DDC2B
mode, the host may access the EEPROM directly. Software can test the HSCL condition by reading the
BUSY flag, which is set in case HSCL=0. A summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM
1. Write the EEPROM slave address to MBUF (bit 0 = 0).
2. Set the S bit to Start.
3. After MTV112M transmits this byte, an MI interrupt will be triggered.
4. The program can write MBUF to transfer the next byte or set the P bit to Stop.
* Please see the attachments about "Master IIC Transmission Timing".
5.3.2. To Read EEPROM
1. Write the slave address to MBUF (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV112M transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out the useless byte to MBUF to continue the data transfer.
6. After MTV112M receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but setting the P bit before reading can
terminate the operation.
* Please see the attachments about "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL or ISDA/ISCL pins, and selected by the SLVsel
control bit. This block can receive/transmit data using the IIC protocol. S/W may set the SLVADR register to
determine which slave address the block should respond to.
In receiving mode, the block first detects an IIC slave address match condition then issues a SLVMI interrupt.
The data received from SDA is shifted into a shift register and written to the RCBUF latch. The first byte
loaded is the word address (slave address is dropped). This block also generates an RCBI (Receive Buffer
full Interrupt) each time the RCBUF is loaded. If S/W can't read out the RCBUF in time, the next byte will not
be written to RCBUF and the slave block will return NACK to the master. This feature guarantees the data
integrity of communication. A WADR flag can tell S/W if the data in RCBUF is a word address.
In transmission mode, the block first detects an IIC slave address match condition then issues a SLVMI. In
the meantime, the data pre-stored in the TXBUF is loaded into the shift register, results in TXBUF emptying
and generates a TXBI (Transmission Buffer Interrupt). S/W should write the TXBUF a new byte for the next
transfer before the shift register empties. Failure to do this will cause data corruption. The TXBI occurs each
time the shift register receives new data from TXBUF. The SLVMI is cleared by writing the SLVSTUS
register. The RCBI is cleared by reading the RCBUF. The TXBI is cleared by writing the TXBUF.
If the control bit ENSCL is set, the block will hold SCL low until the RCBI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
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