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參數(shù)資料
| 型號： | MTV112M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Flash Version |
| 中文描述： | CRT顯示器8051嵌入式控制器Flash版本 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | MTV112M |
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 12 - 2001/05/18
INTFLG
(w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serving the interrupt routine.
HPRchg= 1
→
No action.
= 0
→
Clears HSYNC presence change flag.
VPRchg= 1
→
No action.
= 0
→
Clears VSYNC presence change flag.
HPLchg= 1
→
No action.
= 0
→
Clears HSYNC polarity change flag.
VPLchg= 1
→
No action.
= 0
→
Clears VSYNC polarity change flag.
HFchg = 1
→
No action.
= 0
→
Clears HSYNC frequency change flag.
VFchg = 1
→
No action.
= 0
→
Clears VSYNC frequency change flag.
VSYNCi= 1
→
No action.
= 0
→
Clears VSYNC interrupt flag.
INTFLG
(r) :
Interrupt flag.
HPRchg= 1
VPRchg= 1
HPLchg= 1
VPLchg= 1
HFchg = 1
VFchg = 1
VSYNCi= 1
→
Indicates an HSYNC presence change.
→
Indicates a VSYNC presence change.
→
Indicates a HSYNC polarity change.
→
Indicates a VSYNC polarity change.
→
Indicates an HSYNC frequency change or counter overflow.
→
Indicates a VSYNC frequency change or counter overflow.
→
Indicates a VSYNC interrupt.
INTEN
(w) :
Interrupt enabler.
EHPR = 1
EVPR = 1
EHPL
= 1
EVPL
= 1
EHF
= 1
EVF
= 1
EVSI
= 1
→
Enables HSYNC presence change interrupt.
→
Enables VSYNC presence change interrupt.
→
Enables HSYNC polarity change interrupt.
→
Enables VSYNC polarity change interrupt.
→
Enables HSYNC frequency change / counter overflow interrupt.
→
Enables VSYNC frequency change / counter overflow interrupt.
→
Enables VSYNC interrupt.
5. DDC & IIC Interface
5.1 DDC1 Mode
MTV112M enters DDC1 mode after Reset. In this mode, VSYNC is used as a data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from 8 bytes FIFO in MTV112M. MTV112M
fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null bit (=1) as
packet separator. The software program should load EDID data (original stored in EEPROM) into FIFO and
take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are fewer than N
(N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO from emptying,
software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand, FIFO sets the FIFOH
flag when its capacity is full. Software should not write additional data to FIFO in such instance. The FIFOI
interrupt can be masked or enabled by an EFIFO control bit. A simple way to control FIFO is to set (LS1,
LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into FIFO each time a FIFOI interrupt
arises. A special control bit "LDFIFO" can reduce the software effort when EDID data is stored in EEPROM.
If LDFIFO=1, FIFO will be automatically loaded with MBUF data when software reads MBUF XFR.
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相關代理商/技術參數(shù) |
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|---|---|
| MTV1-12PAL39 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-12PAL39 - Bulk |
| MTV1-12PCL1-1 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-12PCL1-1 / 097432-0074 / Micro |
| MTV1-12PH001-04 | 制造商:ITT Interconnect Solutions 功能描述:Cable Assembly Pre-Wired Pigtail 0.457m 26AWG 12 POS Micro Strip PIN Crimp |
| MTV1-12PH002-01 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-12PH002-01 - Bulk |
| MTV1-12PH003-01 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-12PH003-01 - Bulk |
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