參數(shù)資料
型號(hào)： MTV112M
廠商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded CRT Monitor Controller Flash Version
中文描述： CRT顯示器8051嵌入式控制器Flash版本
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 160K
代理商： MTV112M
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 16 - 2001/05/18
6. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip
resetting signal. After the power supply is above 4.0V, LVR maintains the reset state for 144 Xtal cycles to
guarantee the chip exit reset condition has a stable Xtal oscillation. The specific time of power supply in a
low level is 3us and is adjustable by an external capacitor connected to the RST pin.
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT (2:0). The timer
function is disabled after power-on reset. The user can activate this function by setting WEN and clear the
timer by setting WCLR.
7. A/D Converter
The MTV112 is equipped with two 4-bit or four 6-bit A/D converters. Each one can be enabled/disabled by
S/W control. The refresh rate for the ADC is OSC freq./6144(4-bit) or OSC freq./12288(6-bit). The ADC
compare the input pin voltage with the internal VDD*N/16(4-bit) or VDD*N/64(6-bit) voltage (where N = 0 -15
or N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/16 or VDD *N/64 and
smaller than VDD*(N+1)/16 or VDD*(N+1)/64.
Reg name
ADC
ADC
ADC
WDT
addr
A0h (w) ENADC
ADCMOD
A0h (r)
AD1b3
A0h (r)
X
80h (w)
WEN
bit7
bit6
bit5
X
AD1b1
ADb5
CLRDDC
DIV253
bit4
X
AD1b0
ADb4
bit3
EADC3
AD0b3
ADb3
DACK
bit2
EADC2
AD0b2
ADb2
WDT2
bit1
EADC1
AD0b1
ADb1
WDT1
bit0
EADC0
AD0b0
ADb0
WDT0
AD1b2
X
WCLR
WDT
(w) :
Watchdog timer control register.
= 1
= 1
CLRDDC
= 1
WDT2: WDT0
= 0
= 1
= 2
= 3
= 4
= 5
= 6
= 7
WEN
WCLR
→
Enables watchdog timer.
→
Clears watchdog timer.
→
Clears DDC2 flag.
→
Overflow interval = 8 x 0.25 sec.
→
Overflow interval = 1 x 0.25 sec.
→
Overflow interval = 2 x 0.25 sec.
→
Overflow interval = 3 x 0.25 sec.
→
Overflow interval = 4 x 0.25 sec.
→
Overflow interval = 5 x 0.25 sec.
→
Overflow interval = 6 x 0.25 sec.
→
Overflow interval = 7 x 0.25 sec.
ADC
(w) :
ADC control.
ENADC
= 1
= 1
→
Enables ADC.
→
4 channels 6 bits ADC are selected.
Note:
Only one ADC input can be enabled at the same time.
→
Dual 4 bits ADC are selected.(ADC1 and ADC0)
→
Enables ADC3 pin input.
→
Enables ADC2 pin input.
→
Enables ADC1 pin input.
→
Enables ADC0 pin input.
ADCMOD
= 0
= 1
= 1
= 1
= 1
EADC3
EADC2
EADC1
EADC0
ADC
(r) :
ADC conversion result.
AD1b3: AD1b0 4-bit ADC1 convert result.
AD0b3: AD0b0 4-bit ADC0 convert result.
ADb5: ADb0
6-bit ADC convert result.
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