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| 型號： | MTD20N03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 20 AMPERES 30 VOLTS RDS(on) = 0.035 OHM |
| 中文描述： | 20 A, 30 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 31/38頁 |
| 文件大?。?/td> | 739K |
| 代理商： | MTD20N03HDL |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
31
34701
TYPICAL APPLICATION
maximum power dissipation, and hence the maximum output
current for the required input-to-output voltage drop. The
power dissipation of the external MOSFET can be calculated
from the simple formula:
Where P
D(Q)
is the power MOSFET power dissipation
VIN is the LDO input voltage,
VLDO is the LDO output voltage,
ILDO is the LDO output load current.
Table 10
shows the recommended power MOSFET types
for the 34701 linear regulator, their typical power dissipation,
and thermal resistance junction-to-case.
NOTE
: Freescale does not assume liability, endorse, or warrant
components from external manufacturers referenced in figures
or tables. Although Freescale offers component
recommendations, it is the customer’s responsibility to validate
their application.
*When mounted to an FR4 using 0.5 sq.in. drain pad size
The maximum power dissipation is limited by the
maximum operating junction temperature T
Jmax
. The
allowed power dissipation in the given application can be
calculated from the following expression:
Where P
D(Q)max
is the power MOSFET maximum
allowed dissipation,
T
Jmax
is the power MOSFET maximum operating
junction temperature,
T
A
is the ambient temperature,
R
thJC
is the power MOSFET thermal resistance
junction-to-case,
R
thCB
is the thermal resistance case-to-board,
R
thBA
is the thermal resistance board-to-ambient of
the PC board.
PCB Layout Considerations
As with any power application, the proper PCB layout
plays a critical role in the overall power regulator
performance. While good careful printed circuit board layout
significantly improves regulation parameters and
electromagnetic compatibility (EMC) performance of the
switching regulator, poor layout practices can lead not only to
significant degradation of regulation and EMC parameters
but even to total dysfunction of the whole regulator IC.
Extreme care should be taken when laying out the ground
of the regulator circuit. In order to avoid any inductive or
capacitive coupling of the switching regulator noise into the
sensitive analog control circuits, the noisy power ground and
the clean quiet signal ground should be well separated on the
printed circuit board, and connected only at one connection
point. The power routing should be made by heavy traces or
areas of copper. The power path and its return should be
placed, if possible, atop each other on the different layers or
opposite sides of the PC board. The switching regulator input
and output capacitors should be physically placed very close
to the power terminals (VIN2, SW, PGND) of the 34701
switching regulator; and their ground terminals, together with
the 34701 power ground terminals (PGND), should be
connected by a single island of the power ground copper to
create the “single-point” grounding.
Figure 32
illustrates the
34701 switching regulator grounding concept. The bootstrap
capacitor C
b
should be tightly connected to the integrated
circuit as well.
Figure 32. 34701 Buck Regulator Layout
The same guidelines as those for the layout of the main
switching buck regulator should be applied to the layout of the
low power auxiliary boost regulator and to some extent, the
power path of the linear regulator.
Table 10. Recommended Power MOSFETs
Part No.
Package
Typ. P
D
R
thJ-C
IRL2703S
D2PAK
2.0 W
3.3 °C/W
MTD20N03HDL
DPAK
1.75 W*
1.67 °C/W
P
D Q
I
LDO
V
IN
V
LDO
–
(
)
×
=
P
D Q
max
T
R
thCB
+
A
+
R
thJC
R
thBA
-------------------------------–
≤
SW
PGND
INV
Vout = 1.5 V
GND
BOOT
VBST
VIN2
Cb
Vin = 5.0 V
Vout Return
Signal
Ground
Power
Ground
To Load
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