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參數(shù)資料
| 型號： | MTD20N03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 20 AMPERES 30 VOLTS RDS(on) = 0.035 OHM |
| 中文描述： | 20 A, 30 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 16/38頁 |
| 文件大小： | 739K |
| 代理商： | MTD20N03HDL |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
16
34701
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
POWER SUPPLY TERMINAL (VDDI)
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or
X7R capacitor is recommended.
ADDRESS TERMINAL (ADDR)
The ADDR terminal is used to set the address of the
device when used in an I
2
C communication. This terminal
can either be tied to VDDI or grounded through a 10 k
resistor. Refer to
I
2
C Bus Operation on page 26
for more
information on this terminal.
ENABLE 1 AND 2 TERMINALS (EN1 AND EN2)
These two terminals permit positive logic control of the
Enable function and selection of the Power Sequencing
mode concurrently.
Table 5
depicts the EN1 and EN2
function and Power Sequencing mode selection.
Both EN1 and EN2 terminals have internal pulldown
resistors and both can withstand a short circuit to the supply
voltage, 6.0 V.
RESET TIMER TERMINAL (RT)
The Reset Timer power-up delay (RT) terminal is used to
set the delay between the time when the LDO and switcher
outputs are active and stable and the
RST
output is released.
An external resistor and capacitor are used to program the
timer. The power-up delay can be obtained by using the
following formula:
t
D
= 10 ms + R
t
C
t
Where R
t
is the Reset Timer programming resistor and C
t
is the Reset Timer programming capacitor, both connected in
parallel from RT to ground.
Note
Observe the maximum C
t
value and expect reduced
accuracy if R
t
is less than 10 k
.
RESET OUTPUT TERMINAL (
RST
)
The Reset Control circuit monitors both the switching
regulator and the LDO feedback voltages. It is an open drain
output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
The Reset Control circuit supervises both output
voltages—the linear regulator output V
LDO
and the switching
regulator output V
OUT
. When either of these two regulators
is out of regulation (high or low), the
RST
terminal is pulled
low. There is a 20
μ
s delay filter preventing erroneous resets.
During power-up sequencing,
RST
is held low until the Reset
Timer times out.
CLOCK SELECTION TERMINAL (CLKSEL)
This terminal sets the CLKSYN terminal as either an
oscillator output or a synchronization input terminal. The
CLKSEL terminal is also used for the I
2
C address selection.
CLOCK SYNCHRONIZATION TERMINAL (CLKSYN)
Oscillator output/synchronization input terminal.
Table 5.
Operating Mode Selection
EN1
EN2
Operating Mode
0
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
1
No Power Sequencing,
Regulators Enabled
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