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| 型號(hào)： | MTD20N03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 20 AMPERES 30 VOLTS RDS(on) = 0.035 OHM |
| 中文描述： | 20 A, 30 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大小： | 739K |
| 代理商： | MTD20N03HDL |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
26
34701
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
I
2
C BUS OPERATION
The 34701 device is compatible with the I
2
C interface
standard. SDA and SCL terminals are the Serial Data and
Serial Clock terminals of the I
2
C bus.
I
2
C COMMAND AND DATA FORMATS
Communication Start
Communication starts with a START condition, followed by
the slave device unique address. The Read/Write (R/W) bit
defines whether the data should be read from or written to the
device (the 34701 operates only as a slave device; therefore,
the R/W bit should always be set to 0). The 34701 responds
by sending the Acknowledge bit (Ack) to the master device.
Figure 20
illustrates the beginning of an I
2
C communication
for a 7-bit slave address.
Figure 20. Communication Start Using 7-Bit Address
Slave Address Definition
34701 has the two least significant address bits (LSB)
defined by the state of the CLKSEL terminal (A1) and the
ADDR terminal (A0).
Note
The state of the CLKSEL terminal also defines the
configuration of the oscillator synchronization CLKSYN
terminal. Leaving the CLKSEL terminal open or pulling it high
defines the CLKSYN terminal as an oscillator output. When
the CLKSEL terminal is pulled low, the CLKSYN terminal is
configured as a synchronization input for the external clock
signal.
This feature allows up to four 34701 ICs to communicate
in the same I
2
C bus, all of them sharing the same high-order
address bits. A different combination of the two LSB address
bits A1 and A0 can be assigned to each individual part to
assure its unique address.
Figure 21
illustrates the flexible
addressing feature for a 7-bit address.
Table 6
provides the
definition of the selectable portion of the device address.
When the ADDR terminal is used and put to low level, pull
the ADDR terminal to ground through a 10 k
resistor.
Figure 21. Address Bit Definition for 7-Bit Address
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA
can be written into the slave registers. The R/W bit must be
set to 0 to allow DATA to be written into the 34702.
Figure 22
shows the data write sequence. Actions performed by the
slave device are grayed.
Figure 22. Data Transfer for Write Operations
DATA Definition
The DATA field in the single Data Transfer contains one or
several Command Bytes. The Command Byte identifies the
kind of operation required by the master to be performed and
has two fields, as illustrated in
Figure 23
:
1. Address field
2. Value field
The address field is selected from the list in
Table 7
.
Figure 23. Command Byte
Refer to
Table 8
, page
27
, which summarizes the value
field definitions for the entire set of operation options.
S
7-Bit Address
R/W
Ack
Bits
Fixed Address Selectable
Address
1
0
2
3
5
6
1
1
1
0
1
A1 A0
4
MSB
LSB
Table 6.
Definition of Selectable Portion of Device
Address
CLKSEL
Terminal
ADDR Terminal
A1
A0
Low
Low
0
0
Low
High (Open)
0
1
High (Open)
Low
1
0
High (Open)
High (Open)
1
1
Table 7.
Address Field Definitions
Address Field
Operation
Write
001
Voltage Margining
W
011
Watchdog
W
S
7-Bit Address
0
Ack
DATA
Ack
(Write)
D6 D5 D4 D3
D1 D0
Address Field
Value Field
7
D7
D2
3
2
1
0
4
5
6
Bits
MSB
LSB
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