參數(shù)資料
型號(hào)： MT90883
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁(yè)數(shù)： 72/97頁(yè)
文件大?。?/td> 702K
代理商： MT90883
MT90880/1/2/3
Data Sheet
72
Zarlink Semiconductor Inc.
6.11.1 DMA Descriptor Rings and Lists
Data for transfer to and from the MT90880 is held in a Descriptor Ring or List data structure in system memory
(see Figure 33 and Figure 34). Once the CPU has set up the descriptor structure, the DMA engine is simply told
where to find the head descriptor. The DMA engine co-ordinates the transfer of packets to and from the data
structures with minimal further CPU intervention.
The "ring" data structure (Figure 33) allows a circular buffer to be created. Once the descriptors have been set
up, they should never need re-programming, save to change the relevant status and command bits. The ring
data structure is useful when a finite size buffer is allocated for packet transfer.
Figure 33 - Descriptor Ring Structure
A list structure (Figure 34) may also be used. This is similar to the ring, but final link pointer does not point back
to the head descriptor. This is useful where a more elastic buffer is required, but requires more CPU
intervention, since once the list has completed, it is necessary to re-program the DMA to point to the next set of
descriptors.
Link
Command
Buffer Pointer
Status
Data Buffer
Head Descriptor
Link
Command
Buffer Pointer
Status
Data Buffer
Link
Command
Buffer Pointer
Status
Data Buffer
Link
Command
Buffer Pointer
Status
Data Buffer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90883A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT9088IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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