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參數(shù)資料
| 型號： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 42/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883 |
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MT90880/1/2/3
Data Sheet
42
Zarlink Semiconductor Inc.
Figure 20 - Connecting to Framers in Synchronous Master Mode
The MT90880 may also be used as a TDM backplane master, such as an H.100/H.110 bus (reference 8), or an
H-MVIP backplane (reference 9). The integrated DPLL provides a very stable, low jitter timing reference
suitable for use as the master timing source for a backplane, with automatic, low MTIE failover from primary to
secondary reference in the event of a reference failure.
Synchronous Slave Mode
In
synchronous slave mode
, the MT9088x accepts a clock from the WAN, rather than mastering the clock. One
of the 32 incoming ports is chosen to provide the primary timing reference, and its clock and frame pulse are
used directly to clock the data in and out on all 32 streams, bypassing the DPLL output. Again, a secondary
reference port may be chosen, and this is automatically switched in if the primary fails. Unused clock and frame
inputs may be left unconnected, as all inputs are connected to an internal 100 K
pull-down resistor to prevent
them from floating.
A typical application for this configuration is to connect to a TDM backplane, where the MT9088x is used as a
backplane slave device. An example of this is Figure 21, which shows an MT90880 connected as a backplane
slave to an H.100/H.110 TDM backplane (reference 8). An MT90866 TDM switch device is shown interfacing
the MT90880 to the backplane. Up to three MT90880 devices could be connected directly to a single MT90866
switch. The CT_C8_A and CT_C8_B backplane clocks are used as the primary and secondary master clocks to
MT9076
Combined
Framer-LIU
DO
DI
C4b
F0b
MT90880
TDM-IP Processor
WAN_STI0
WAN_STO0
DPLL
Master Clock Output
ST-Bus 2.048Mbit/s mode
MUX
WAN_CLKI0
WAN_FRMI0
T1 or E1 line
RxFP
WAN_STI1
WAN_STO1
WAN_CLKI1
WAN_FRMI1
WAN_STI31
WAN_STO31
WAN_CLKI31
WAN_FRMI31
8 KHz
8 KHz
8 KHz
WAN_CLKO
WAN_FRMO
4.096 MHz
8 KHz
internally used
TDM clock and frame
MT9076
Combined
Framer-LIU
DO
DI
C4b
F0b
T1 or E1 line
RxFP
MT9076
Combined
Framer-LIU
DO
DI
C4b
F0b
T1 or E1 line
RxFP
相關PDF資料 |
PDF描述 |
|---|---|
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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