參數(shù)資料
型號： MT90883
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 28/97頁
文件大?。?/td> 702K
代理商： MT90883
MT90880/1/2/3
Data Sheet
28
Zarlink Semiconductor Inc.
5.2 Basic Operation
A diagram of the MT90880 device is given in Figure 10, which shows the major data and control flows between
functional components.
Figure 10 - MT90880 Data and Control Flows
5.2.1 WAN Access Interface
The WAN Access Interface consists of up to 32 ports, each with an input an output data stream operating at
2.048 Mbs. Alternatively, it can be configured as 8 ports operating at 8.192 Mbs. All 32 ports can operate using
a common clock (synchronous mode) or using an independent clock for each port (asynchronous mode). When
operating synchronously, the device can either operate as a slave, accepting an external clock, or as a master,
supplying the clock to the devices on the WAN Access Interface from its internal Stratum 4E DPLL. The master
clock can be locked to any of the incoming 32 frame references.
5.2.1.1 TDM Packet Assembly
Data traffic received on the WAN Access Interface is sampled in the WAN Interface block. It is then forwarded
either to the WAN Receive block for packet assembly, or out to the TDM switch. The switch can be used both for
re-ordering timeslots before packet assembly, or to divert traffic out of the local TDM interface for processing in
a local resource pool (e.g. a DSP or other data processing unit).
The WAN Receive block can handle up to 128 active virtual channels or “contexts” simultaneously. A context
may contain any number of timeslots, from 1 to 1024. This is known as “N x 64 Kbs” trunking. Timeslots may be
added or deleted dynamically from a context to optimize network bandwidth utilization.
Dual Packet
Interface
MAC
W
3
P
D
WAN
Transmit
WAN
Receive
WAN
Interface &
Multiplexer
Host Control/Data Interface
32 bit, 33 MHz PCI
Memory Manager and
SSRAM Interface Controller
Packet Memory
0.125 - 8 MBytes SSRAM
(Burst or ZBT type)
Queue
Manager
Packet
Receive
Packet
Transmit
PCI Interface
DMA
Control
Admin.
Local TDM Interface
32 ports at 2, 4, or 8 Mbit/s
1K Switch
DPLL
JTAG Test
Controller
JTAG Interface
Data Flows
Control Flows
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90883A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT9088IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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