- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359235 > MT90883 (Zarlink Semiconductor Inc.) TDM to Packet Processors PDF資料下載
參數(shù)資料
| 型號： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 19/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
MT90880/1/2/3
Data Sheet
19
Zarlink Semiconductor Inc.
Table 12 - Test Facilities
3.7.3 Test Operating Modes
1) Normal operating mode (T_MODE[1:0] = '11')
The device samples the T_D pins to determine the required operating mode shortly after reset is released.
These pins are known as the "bootstrap controls". The device has internal pull-up (100 K
±
30%) resistors
connected to the T_D bus pins. To pull-low connect a 10 K
pull-down resistor to ground. Bootstrap controls
are as follows:
Table 13 - Bootstrap Pin Functions
iddq
I
AD23
IDDQ test enable.
Set low for normal operation.
sclk_AT1
O
B26
Analog test output for system clock
PLL. Leave unconnected in normal
operation.
pclk_AT1
O
AF24
Analog test output for PCI clock PLL.
Leave unconnected in normal
operation.
ram_clk
O
Y2
66 MHz memory clock output.
This is used for test purposes only.
Leave unconnected in normal
operation.
T_D
Function
Notes
15
Reserved
14
Reserved
Pull low for normal operation.
13:11
Reserved
10:8
Selects delay of RAM_CLK output relative to
S_CLK.
Leave unconnected in normal operation.
7
Pull low to bypass PCI_CLK PLL.
Leave unconnected in normal operation.
6
Pull low to bypass the S_CLK PLL.
Leave unconnected in normal operation.
5
Controls m_mint0 and m_mint1 polarity - pull low
for active low and leave unconnected for active
high.
See Table 21.
4
Pull low to enable RAM_CLK output (otherwise it
will be high impedance).
Leave unconnected in normal operation.
3
Pull low for freeze enable.
Leave unconnected in normal operation.
2
Pull low for simulation speed-up.
This reduces the number of cycles that the chip is
held in reset after S_RST# and PCI_RST# have
gone high from 16348 to 256.
This should not be used during normal operation,
since the PLLs will not have time to lock.
Leave unconnected in normal operation.
0:1
Reserved
Signal
I/O
Width
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。