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MT90880/1/2/3
Data Sheet
20
Zarlink Semiconductor Inc.
2) Board level continuity test mode (T_MODE[1:0] = '10')
In continuity test mode the core of the chip is held in reset. Pin T_D[10] selects the board level test mode.
3) Scan test mode (T_MODE[1:0] = '01')
System clock and PCI clock PLLs are put into bypass mode. The core PCI and system resets are driven directly
from the pins i.e. the logic which holds the resets asserted until the PLLs have had time to lock is disabled.
4) PLL test mode (T_MODE[1:0] = '00')
The core of the chip is held in reset. Test bus pins are configured for direct test access to the system clock and
PCI clock PLLs.
3.8 Power and Ground Connections
Table 14 - Power and Ground Connections
4.0 Typical Applications
4.1 Packet Backplane Interconnection
The MT9088x family can be used to entirely replace the TDM backplane infrastructure in a conventional computer
telephony system with a packet backplane. This has several advantages: it is easily scalable, eliminates the timing
problems in passing large TDM buses around the system, uses readily available and low-cost network hardware,
and simplifies the provision of new services to customers. This type of structure can be used in applications as
diverse as telephone switches, multi-service access platforms and voice over IP gateways. Figure 2 shows a
multi-service access platform based on an Ethernet backplane using the MT90880.
Signal
Package Balls
Description
VDD33
AA5, AA22, AB5, AB6, AB13, AB14, AB21, AB22, E5, E6,
E13, E14, E21, E22, F5, F22, M5, N5, N22, P5, P22, R22
3.3 V VDD power supply
VDD18
AA3, E2, F24, H23, J3, L1, M26, P23, R2, V3, W22, Y26
1.8 V VDD power supply
GROUND
L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15,
M16, N11, N12, N13, N14, N15, N16, P11, P12, P13,
P14, P15, P16, R11, R12, R13, R14, R15, R16, T11, T12,
T13, T14, T15, T16, AD25, E23
0 V power supply
A1VDD
D25
1.8 V VDD power supply
A2VDD
AF25
1.8 V VDD power supply
no connection
D23, AC16