參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù)： 72/86頁(yè)
文件大小： 701K
代理商： MT90866AG2
MT90866
Data Sheet
72
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 28 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 29 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 30 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
AC Electrical Characteristics
- Reference Output Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
3
4
5
NREFo Output Delay Time
NREFo Clock Period
NREFo Clock High Time
NREFo Clock Low Time
NREFo Clock Rise/Fall Time
t
ROD
t
RP
t
RH
t
RL
t
rREF
,
t
fREF
t
R8KOP
t
R8KO2H
t
R8KO2L
t
R8KO15H
t
R8KO15L
20
ns
(DIV1,DIV0) =
(0,0)
in the DOM2
Register
Same as LREF0-7 Period
Same as LREF0-7 High Time
Same as LREF0-7 Low Time
0
12
14
ns
6
7
8
9
10 NREFo Clock Low Time
NREFo Clock Period
NREFo Clock High Time
NREFo Clock Low Time
NREFo Clock High Time
124.9
124.4
488-
124.3
648-
125
124.5
488
124.4
648
125.1
124.6
488+
124.5
648+
μ
s
μ
s
ns
μ
s
ns
(DIV1,DIV0) =
(0,1) or
(DIV1,DIV0) =
(1,0)
in the DOM2
Register
LREF0-7
(8 KHz)
t
fREF
t
rREF
NREFo
(8 KHz)
t
RL
t
RP
t
t
ROD
LREF0-7
(2.048 MHz)
t
fREF
t
rREF
t
RP
NREFo
(2.048 MHz)
t
RL
t
RH
t
ROD
LREF0-7
(1.544 MHz)
t
fREF
t
rREF
t
RP
t
RL
t
RH
t
ROD
NREFo
(1.544 MHz)
LREF0-7
(2.048 MHz)
NREFo
(8 KHz)
t
R8KO2H
t
R8KO2L
t
R8KOP
t
ROD
t
fREF
t
rREF
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