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參數(shù)資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 25/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
25
Zarlink Semiconductor Inc.
12.0 Backplane Connection Memory
The backplane connection memory controls the switching configuration of the backplane interface. Locations in the
backplane connection memory are associated with particular STio streams.
The BTM2 - 0 bits of each backplane connection memory allows the per-channel selection for the message or the
connection mode, the constant or the variable delay mode, the high impedance control of the STio driver or the bit
error test enable. See Table 25 on page 63 for the content per-channel control function.
In the switching mode, the contents of the backplane connection memory stream address bits (BSAB4-0) and
channel address bits (BCAB7-0) define the source information (stream and channel) of the time slot that will be
switched to the backplane STio streams. During the message mode, only the lower 8 bits (8 least significant bits) of
the backplane connection memory will be transferred to the STio pins.
13.0 Local Connection Memory
The local connection memory controls the local interface switching configuration. Local connection memory is split
into a high and a low part. Locations in the local connection memory are associated with particular STo output
streams.
The LTM2 - 0 bits of each local connection memory low allows the per-channel selection for the message or the
connection mode, the constant or the variable delay mode, the high impedance control of the STo driver or the bit
error test enable. See Table 29 on page 65 for the content per-channel control function.
In the switching mode, the contents of the local connection memory low stream address bits (LSAB4-0) and the
channel address bits (LCAB7-0) of the local connection memory defines the source information (stream and
A13
(Note 1)
Stream Address (ST0-31)
Channel Address (Ch0-255)
A12
A11
A10
A9
A8
Stream #
A7
A6
A5
A4
A3
A2
A1
A0
Channel #
1
1
1
1
1
1
1
1
1
.
.
.
.
.
.
1
1
1
1
1
0
0
0
0
0
0
0
0
0
.
.
.
.
.
.
1
1
1
1
1
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
1
1
1
1
1
0
0
0
0
1
1
1
1
0
.
.
.
.
.
.
0
1
1
1
1
0
0
1
1
0
0
1
1
0
.
.
.
.
.
.
1
0
0
1
1
0
1
0
1
0
1
0
1
0
.
.
.
.
.
.
1
0
1
0
1
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
.
.
.
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
0
0
.
.
0
0
0
0
.
.
0
0
.
.
0
0
.
.
1
1
0
0
.
.
0
0
0
0
.
.
0
0
.
.
1
1
.
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
.
.
0
1
.
.
0
1
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3 & 6)
.
.
Ch 126
Ch 127 (Note 4 & 7)
.
.
Ch 254
Ch 255 (Note 5)
Notes:
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2 Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4 Mb/s.
4. Channels 0 to 127 are used when serial stream is at 8 Mb/s.
5. Channels 0 to 255 are used when serial stream is at 16 Mb/s.
6. Channels 0 to 63 are used when local serial stream is in 4-bit wide sub-rate switching mode.
7. Channels 0 to 127 are used when local serial stream is in 2-bit wide sub-rate switching mode.
Table 8 - Address Map for Memory Locations (A13 = 1)
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