參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù)： 53/86頁
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
53
Zarlink Semiconductor Inc.
Figure 21 - Local Output Advancement Timing
Name
Description
LOAn1,
LOAn0
(See Note 1)
Local Output Advancement Bits 1-0:
These two bits represent the amount of offset
that a particular stream output can be advanced. When the offset is zero, the serial
output stream has normal alignment with the frame pulse.
Note 1: n denotes a STi stream number from 0 to 27.
Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits
Read/Write Addresses:
0020
H
for LOAR0 register,
0022
H
for LOAR2 register,
0000
H
for all LOAR registers.
0021
H
for LOAR1 register,
0023
H
for LOAR3 register,
Reset value:
15
14
LOA
70
13
LOA
61
12
LOA
60
11
LOA
51
10
LOA
50
9
8
7
6
5
4
3
2
1
0
LOAR0 LOA
71
LOA
41
LOA
40
LOA
31
LOA
30
LOA
21
LOA
20
LOA
11
LOA
10
LOA
01
LOA
00
LOAR1 LOA
151
LOA
150
LOA
141
LOA
140
LOA
131
LOA
130
LOA
121
LOA
120
LOA
111
LOA
110
LOA
101
LOA
100
LOA
91
LOA
90
LOA
81
LOA
80
LOAR2 LOA
231
LOA
230
LOA
221
LOA
220
LOA
211
LOA
210
LOA
201
LOA
200
LOA
191
LOA
190
LOA
181
LOA
180
LOA
171
LOA
170
LOA
161
LOA
160
LOAR3
0
0
0
0
0
0
0
0
LOA
271
LOA
270
LOA
271
LOA
260
LOA
251
LOA
250
LOA
241
LOA
240
LOAn1
LOAn0
Output
Advancement
C8_A_io
or C8_B_io
period
2.048Mb/s
(bit)
4.096Mb/s
(bit)
8.192Mb/s
(bit)
0
0
0 ns
0
0
0
0
0
1
- 7.5 ns
- 1/16
- 1/64
- 1/32
- 1/16
1
0
- 15 ns
- 1/8
- 1/32
- 1/16
- 1/8
1
1
- 22.5 ns
- 3/16
- 3/64
- 3/32
- 3/16
C64
8 Mb/s Stream
8 Mb/s Stream
advancement is 0 ns
LOA=00
advancement is 7.5 ns
LOA=01
Bit 7
Bit 7
8 Mb/s Stream
advancement is 15 ns
LOA=10
Bit 7
8 Mb/s Stream
advancement is 22.5 ns
LOA=11
Bit 7
denotes the starting point of the bit cell
(internal clock)
ST_FPo0/1
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