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參數(shù)資料
| 型號(hào)： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 40/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
40
Zarlink Semiconductor Inc.
The CT_FRAME and the CT_C8 are required clocks. C1M5o is provided as an output clock of the MT90866.
The duty cycle of all output signals is independent of the duty cycle of the device master clock, C20i. The CT_C8,
C2M and C1M5o clocks have nominal 50% duty cycle,
The output frame pulse (CT_FRAME) is generated in such a way that it is always aligned with the CT_C8 clock to
form the required H.110 CT Bus clock and frame pulse shape (when the CT_FRAME is low the rising edge of the
CT_C8 defines the frame boundary). Depending on the selected input reference frequency, the CT_FRAME is
generated in the following way:
When the input reference frequency is 8 kHz, the output frame pulse is aligned with the rising edge of the
reference.
When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the
output frame boundary, always keeping the described relation to the CT_C8 clock.
When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the
input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io)
is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input
to the Divider circuit and the CT_FRAME is synchronized to it.
18.9 Frequency Select MUX Circuit
According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be
the feedback signal to the PLL and MTIE Circuits.
18.10 Modes of Operation
The DPLL can operate in two main modes: the Normal and the Holdover Mode. Each of these modes has two
states: the primary or the secondary state. The state depends on which reference is currently selected as the
preferred reference the PRI_REF or the SEC_REF. When the DPLL is in the Holdover Mode and the HRST bit of
the DOM2 register is pulsed logic high (or held high continuously), the DPLL operates in Freerun Mode.
18.10.1 Normal Mode
Normal Mode is typically used when a clock source synchronized to the network is required.
In the Normal Mode, the DPLL provides timing (C64, CT_C8, C2M and C1M5o) and frame synchronization
(CT_FRAME) signals which are synchronized to one of two input references (PRI_REF or SEC_REF). The input
reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz.
From a device reset condition or after reference switch, the DPLL can take up to 50 seconds to phase lock the
output signals to the selected input reference signal.
18.10.2 Holdover Mode
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted.
If the FDM1-0 bits are programmed to ‘01’ in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the
DPLL is in the Holdover Mode. The DPLL can also be in the Holdover Mode if the FDM1-0 bits are programmed to
‘00’ and the SLS and PLS bit are observed as ‘11’ in the DPLL House Keeping Register (DHKR).
In the Holdover Mode, the DPLL provides timing and synchronization signals which are based on storage
techniques and are not locked to an external reference signal. The storage value is determined while the device is
in Normal Mode and locked to an external reference signal. When the DPLL is in the Normal Mode and locks to the
input reference signal, a numerical value corresponding to the DPLL output reference frequency is stored
alternately in two memory locations every 32 ms. When the device is switched into the Holdover Mode, the value in
memory from between 32 ms and 64 ms is used to set the output frequency of the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90869 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX) |
| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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