參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 26/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
26
Zarlink Semiconductor Inc.
channel) of the time slot that will be switched to the local STo streams. During the message mode, only the lower 8
bits (8 least significant bits) of the local connection memory low bits are transferred to the STo pins.
In the sub-rate switching mode, although the output channels are divided up into 2 or 4-bit channels, the input
streams still have 8-bit channel boundaries. Therefore, it is necessary to indicate which bits in the input 8-bit
channel will be switched out to the 2 or 4-bit channel. When 2-bit or 4-bit sub-rate switching is enabled, the
LSRS1-0 bits in the local connection memory high define which bit positions contains the sub-rate data.
14.0 Bit Error Rate Test
The MT90866 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The
circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the
BER patterns independently. The transmitter can output a pseudo random patterns of the form 2
15
- 1 to any
channel and any stream within a frame time. For the test, users can program the output channel and stream
through the backplane or local connection memory and the input channel and stream using Local or Backplane
BER Input Selection (BIS) registers. See Table 16 on page 54 and Table 18 on page 54 for the LBIS and the BBIS
registers contents, respectively.
The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the
comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the
Local BER register (LBERR).
15.0 External Tristate Control
The MT90866 has the flexibility to provide users with the choice of external per-channel tristate control. Two control
signals are provided. For the backplane interface, it is the BCSTo output. For the local interface, it is the LCSTo
output. Each control signal has a data rate of 32.768 Mb/s with 4,096 control bits per frame. Each bit position
corresponds to a specific output stream and channel location. When the control bit is high, the corresponding
output channel is in the high impedance state, whereas when the control bit is low, the corresponding output
channel has active output data.
15.1 BCSTo Control Stream
When the STio0-31 streams are in the 8 Mb/s mode, the STio0_Ch0 control bit of the BCSTo stream is advanced by
thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 6, "Backplane Control
(BCSTo) Timing when the STio data rate is 8 Mb/s" on page 26 for the BCSTo control bit pattern.
When the STio0-15 streams are in the 16 Mb/s mode, the STio0_Ch0 control bit of the BCSTo is advanced by
thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 7, "Backplane Control
(BCSTo) Timing when the STio data rate is 16 Mb/s" on page 27 for the BCSTo control bit pattern.
Figure 6 - Backplane Control (BCSTo) Timing when the STio data rate is 8 Mb/s
BCSTo0
Thirty-six c32o cycles
c32o
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
C8_A_io,
C8_B_io
Frame
Boundary
Frame
Boundary
(8 Mb/s Mode)
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