參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù)： 35/86頁(yè)
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
35
Zarlink Semiconductor Inc.
17.2 PRI and SEC MUX Circuits
The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1
bits of the DOM2 Register. If FDM1-0 is ’10’ then the Primary reference is always used regardless of failures. If
FDM1-0 is ’11’ then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in
one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set
to low in the DOM2 register ‘00’, the DPLL is in the Autodetect Mode. In this mode, the outputs from the Reference
Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is set to high
and FDM1 bit is set to low ‘01’, the DPLL is in the Manual Detection Mode and the LOS_PRI and LOS_SEC signals
are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine Circuit. See Table 21 on
page 58 for selection of the Failure Detection Modes.
17.3 Frame Select MUX
When the “A Clocks” or the “B Clocks” are selected as the input reference, an 8.192 MHz clock (either C8_A_io or
C8_B_io) is provided to be the input reference to the PLL circuit (REF). Because the output frame pulse
(CT_FRAME) must be aligned with the selected input frame pulse, the appropriate frame pulse (either
FRAME_A_io or FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit
(FRAME).
17.4 CT Clock and Frame Monitor Circuits
The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the
FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a
tolerance of +/- 35 ns measured between rising edges. If C8 falls outside the range of [87 ns,157 ns], the clock is
rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to
the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or
FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B
signal returns to logic low.
17.5 Reference Monitor Circuits
There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary
reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting
up the appropriate fail outputs (FAIL_PRI and FAIL_SEC). These fail signals are used in the Autodetect mode as
the LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating a failure
depends on the selected reference.
When the selected reference frequency is 8.192 MHz (“A Clocks” or “B Clocks”), the fail signals are passed through
from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly as FAIL_PRI and
FAIL_SEC, accordingly.
For all other reference frequencies (8 kHz, 1.544 MHz and 2.048 MHz), the following checks are performed:
For all references, the “minimum 90 ns” check is done. This is required by the H.110 specifications - both low
level and high level of the reference must last for minimum 90 ns each.
The “period in the specified range” check is done for all references. The length of the period of the selected
input reference is checked if it is in the specified range. For the E1 (2.048 MHz clock) or the T1 (1.544 MHz
clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined clock period
which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8KHz reference, the variation is from 1 +/-
1/32 period.
If the selected reference is E1 or T1, “64 periods in the specified range” check is done. The selected
reference is observed for a long period (64 reference clock cycles) and checked if it is within the specified
range - from 62 to 66 clock periods.
相關(guān)PDF資料
PDF描述
MT90869 Flexible 16K Digital Switch (F16kDX)
MT90869AG Flexible 16K Digital Switch (F16kDX)
MT90870 Flexible 12 k Digital Switch (F12kDX)
MT90871AV Flexible 8K Digital Switch (F8KDX)
MT90871 Flexible 8K Digital Switch (F8KDX)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90866AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch
MT90868AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays
MT90868AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays
MT90869 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX)
MT90869AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*