參數(shù)資料
型號: MT90820
廠商: Mitel Networks Corporation
英文描述: Large Digital Switch(大數(shù)字開關(guān))
中文描述: 大型數(shù)字交換(大數(shù)字開關(guān))
文件頁數(shù): 9/33頁
文件大?。?/td> 132K
代理商: MT90820
CMOS
MT90820
9
The control register is used to control switching
operations in the MT90820. It selects the internal
memory locations that specify the input and output
channels selected for switching.
The data in the control register consists of the
memory block programming bit (MBP), the memory
select bit (MS) and the stream address bits (STA).
The memory block programming bit allows users to
program the entire connection memory block, (see
Memory Block Programming section). The memory
select bit controls the selection of the connection
memory or the data Memory. The stream address
bits
define
an
internal
corresponding to input or output ST-BUS streams.
memory
subsections
The data in the IMS register consists of block
programming
bits
program-ming enable bit (BPE), output stand by bit
(OSB), start frame evaluation bit (SFE) and data rate
selection bits (DR0, DR1). The block programming
and the block programming enable bits allows users
to program the entire connection memory, (see
Memory Block Programming section). If the ODE pin
is low, the OSB bit enables (if high) or disables (if
low) all ST-BUS output drivers. If the ODE pin is high,
the contents of the OSB bit is ignored and all
ST-BUS output drivers are enabled.
(BPD0-BPD4),
block
Connection Memory Control
The contents of the CSTo bit of each connection
memory location are output on the CSTo pin once
every frame. The CSTo pin is a 4.096, 8.192 or
16.384 Mb/s output, which carries 512, 1,024 or
2,048 bits, respectively. If the CSTo bit is set high,
the corresponding bit on the CSTo output is
transmitted high. If the CSTo bit is low, the
corresponding bit on the CSTo output is transmitted
low. The contents of the CSTo bits of the connection
memory are transmitted sequentially on to the CSTo
pin and are synchronous with the data rates on the
other ST-BUS streams.
The CSTo bit is output one channel before the
corresponding channel on the ST-BUS. For example,
in 2Mb/s mode, the contents of the CSTo bit in
position 0 (STo0, CH0) of the connection memory is
output on the first clock cycle of channel 31 through
CSTo pin. The contents of the CSTo bit in position 32
(STo1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CSTo pin.
If the ODE pin or the OSB bit is high, the OE bit of
each connection memory location enables (if high) or
disables (if low) the output drivers for an individual
ST-BUS output stream and channel. See Table 5 for
detail.
The message channel (MC) bit of the connection
memory enables (if high) an associated ST-BUS
output channel in message mode. If the MC bit is
low, the contents of the stream address bit (SAB)
and the channel address bit (CAB) of the connection
memory defines the source information (stream and
channel) of the time-slot that will be switched to the
output. When message mode is enabled, only the
Table 2 - Variable Throughput Delay Value
Table 3 - Constant Throughput Delay Value
Input Rate
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
m < n
m = n, n+1, n+2
m > n+2
2.048 Mb/s
32 - (n-m) time-slots
m-n + 32 time-slots
m-n time-slots
4.096 Mb/s
64 - (n-m) time-slots
m-n + 64 time-slots
m-n time-slots
8.192 Mb/s
128 - (n-m) time-slots
m-n + 128 time-slots
m-n time-slots
Input Rate
Delay for Constant Throughput Delay Mode
(m - output channel number)
(n - input channel number))
2.048 Mb/s
32 + (32 - n) + (m - 1) time-slots
4.096 Mb/s
64 + (64 - n) + (m- 1) time-slots
8.192 Mb/s
128 + (128 - n) + (m- 1) time-slots
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參數(shù)描述
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