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參數(shù)資料
| 型號： | MT90820 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Large Digital Switch(大數(shù)字開關(guān)) |
| 中文描述： | 大型數(shù)字交換（大數(shù)字開關(guān)） |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 132K |
| 代理商： | MT90820 |
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MT90820
CMOS
8
throughput delay capabilities on the per-channel
basis.
For
voice
application,
throughput delay to ensure minimum delay between
input and output data. In wideband data applications,
select constant throughput delay to maintain the
frame integrity of the information through the switch.
select
variable
The delay through the device varies according to the
type of throughput delay selected in the V/C bit of the
connection memory.
Variable Delay Mode (V/C bit = 0)
The delay in this mode is dependent only on the
combination of source and destination channels and
is independent of input and output streams. The
minimum delay achievable in the MT90820 is three
time-slots. When the input channel data is switched
to the same output channel (channel n, frame p), it
will be output in the following frame (channel n,
frame p+1). The same frame delay occurs if the input
channel n is switched to output channel n+1 or n+2.
When input channel n is switched to output channel
n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for
the MT90820 in the variable delay mode.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all
switching configurations by making use of a multiple
data memory buffer. Input channel data is written
into the data memory buffers during frame n will be
read out during frame n+2.
In the MT90820, the minimum throughput delay
achievable in the constant delay mode will be one
frame. For example, in 2 Mb/s mode, when input
time-slot 31 is switched to output time-slot 0. The
maximum delay of 94 time-slots of delay occurs
when time-slot 0 in a frame is switched to time-slot
31 in the frame. See Table 3.
Microprocessor Interface
The MT90820 provides a parallel microprocessor
interface for non-multiplexed or multiplexed bus
structures. This interface is compatible with Motorola
non-multiplexed and multi-plexed buses.
If the IM pin is low, the MT90820 microprocessor
interface assumes Motorola non-multiplexed bus
mode. If the IM pin is high, the device
micro-processor interface accepts two different
timing modes (mode1 and mode2) which allows
direct connection to multiplexed microprocessors.
The microprocessor interface automatically identifies
the type of micro-processor bus connected to the
MT90820. This circuit uses the level of the DS/RD
input pin at the rising edge of AS/ALE to identify the
appropriate bus timing connected to the MT90820. If
DS/RD is low at the rising edge of AS/ALE, then the
mode 1 multiplexed timing is selected. If DS/RD is
high at the rising edge of AS/ALE, then the mode 2
multiplexed bus timing is selected.
For multiplexed operation, the required signals are
the 8-bit data and address (AD0-AD7), 8-bit Data
(D8-D15), Address strobe/Address latch enable (AS/
ALE), Data strobe/Read (DS/RD), Read/Write /Write
(R/W / WR), Chip select (CS) and Data transfer
acknowledge (DTA). See Figure 13 and Figure 14
for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required
signals are the 16-bit data bus (AD0-AD7, D8-D15),
8-bit address bus (A0-A7) and 4 control lines (CS,
DS, R/W and DTA). See Figure 15 for Motorola
non-multiplexed microport timing.
The MT90820 microport provides access to the
internal registers, connection and data memories. All
locations provide read/write access except for the
data memory and the frame alignment register which
are read only.
Memory Mapping
The address bus on the microprocessor interface
selects the internal registers and memories of the
MT90820. If the A7 address input is low, then the
control (CR), interface mode selection (IMS), frame
alignment (FAR) and frame input offset (FOR)
registers are addressed by A6 to A0 according to
Table 4.
If the A7 is high, then the remaining address input
lines are used to select memory subsections of up to
128 locations corresponding to the maximum
number of channels per input or output stream. The
address input lines and the stream address bits
(STA) of the control register allow access to the
entire data and connection memories.
The control and IMS registers together control all the
major functions of the device. The IMS register
should be programmed immediately after system
power-up to establish the desired switching
configuration as explained in the Serial Data
Interface Timing and Switching Configurations
sections.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90820AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays |
| MT90820AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP |
| MT90820AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820AP1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel |
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