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參數(shù)資料
| 型號： | MT90820 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Large Digital Switch(大數(shù)字開關(guān)) |
| 中文描述： | 大型數(shù)字交換（大數(shù)字開關(guān)） |
| 文件頁數(shù)： | 3/33頁 |
| 文件大?。?/td> | 132K |
| 代理商： | MT90820 |
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CMOS
MT90820
3
Pin Description
Pin #
Name
Description
84
PLCC
100
MQFP
1, 11,
30, 54
64, 75
31, 41,
56, 66,
76, 99
V
SS
Ground.
2, 32,
63
5, 40,
67
V
DD
+5 Volt Power Supply.
3 - 10
68-75
STo8 - 15
ST-BUS Output 8 to 15 (Three-state Outputs):
Serial data Output stream.
These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending
upon the value programmed at bits DR0 - 1 in the IMS register.
12 -
27
81-96
STi0 - 15
ST-BUS Input 0 to 15 (Inputs):
Serial data input stream. These streams may
have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value
programmed at bits DR0 - 1 in the IMS register.
28
97
F0i
Frame Pulse (Input):
When the WFPS pin is low, this input accepts and
automatically identifies frame synchronization signals formatted according to
ST-BUS and GCI specifications. When the WFPS pin is high, this pin accepts a
negative frame pulse which conforms to WFPS formats.
29
98
FE/HCLK
Frame Evaluation / HCLK Clock (Input):
When the WFPS pin is low, this pin is
the frame measurement input. When the WFPS pin is high, the HCLK (4.096MHz
clock) is required for frame alignment in the wide frame pulse (WFP) mode.
31
100
CLK
Clock (Input):
Serial clock for shifting data in/out on the serial streams (STi/o 0 -
15). Depending upon the value programmed at bits DR0 - 1 in the IMS register,
this input accepts a 4.096, 8.192 or 16.384 MHz clock.
33
6
TMS
Test Mode Select (Input):
JTAG signal that controls the state transitions of the
TAP controller. This pin is pulled high by an internal pull-up when not driven.
34
7
TDI
Test Serial Data In (Input):
JTAG serial test instructions and data are shifted in
on this pin. This pin is pulled high by an internal pull-up when not driven.
35
8
TDO
Test Serial Data Out (Output):
JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enable.
36
9
TCK
Test Clock (Input):
Provides the clock to the JTAG test logic. This pin is pulled
high by an internal pull-up when not driven.
37
10
TRST
Test Reset (Input):
Asynchronously initializes the JTAG TAP controller by putting
it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not
driven. This pin should be pulsed low on power-up, or held low, to ensure that the
MT90820 is in the normal functional mode.
38
11
IC
Internal Connection (Input):
Connect to V
SS
for normal operation. This pin must
be low for the MT90820 to function normally and to comply with IEEE 1149
(JTAG) boundary scan requirements. This pin is pulled low internally when not
driven.
39
12
RESET
Device Reset (Schmitt Trigger Input):
This input (active LOW) puts the
MT90820 in its reset state that clears the device internal counters, registers and
brings STo0 - 15 and microport data outputs to a high impedance state. The time
constant for a power up reset circuit must be a minimum of five times the rise time
of the power supply. In normal operation, the RESET pin must be held low for a
minimum of 100nsec to reset the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90820AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays |
| MT90820AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP |
| MT90820AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820AP1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel |
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