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參數(shù)資料
| 型號(hào)： | MT90820 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Large Digital Switch(大數(shù)字開關(guān)) |
| 中文描述： | 大型數(shù)字交換（大數(shù)字開關(guān)） |
| 文件頁(yè)數(shù)： | 10/33頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | MT90820 |
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10
MT90820
CMOS
lower half (8 least significant bits) of the connection
memory is transferred to the ST-BUS outputs.
Bit V/C (Variable/Constant Delay) of each connection
memory location allows the per-channel selection
between variable and constant throughput delay
modes.
If the LPBK bit is high, the associated ST-BUS output
channel data is internally looped back to the ST-BUS
input channel (i.e., data from STo n channel m will
appear in STi n channel m). Note: when LPBK is
activated in channel m STo n+1 (for n even) or STo
n-1 (for n odd), the data from channel m of STi n will
be switched to channel m STo n. The associated
frame delay offset register must be set to zero for
proper operation of the per-channel loopback
function. If the LPBK bit is low, the per-channel
loopback feature is disabled and the device will
function normally.
Initialization of the MT90820
After power up, the contents of the connection
memory can be in any state. The ODE pin should be
held low after power up to keep all ST-BUS outputs in
a high impedance state until the microprocessor has
initialized the switching matrix.
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the switch, and put all other channels
into a high impedance state. This procedure
prevents two ST-BUS outputs from driving the same
stream simultaneously. When this process is
complete,
the
microprocessor
matrices can bring the ODE pin or OSB bit high to
relinquish the high impedance state control to the
OE bit in the connection memory.
controlling
the
Table 4 - Internal Register and Address Memory Mapping
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0
Control Register, CR
0
0
0
0
0
0
0
1
Interface Mode Selection Register, IMS
0
0
0
0
0
0
1
0
Frame Alignment Register, FAR
0
0
0
0
0
0
1
1
Frame Input Offset Register 0, FOR0
0
0
0
0
0
1
0
0
Frame Input Offset Register 1, FOR1
0
0
0
0
0
1
0
1
Frame Input Offset Register 2, FOR2
0
0
0
0
0
1
1
0
Frame Input Offset Register 3, FOR3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 0
Ch 1
.
Ch 30
Ch 31
(
Note 2)
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 62
Ch 63
(
Note 3)
1
1
1
1
1
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 64
Ch 65
.
Ch 126
Ch 127
(
Note 4)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8Mb/s mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90820AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays |
| MT90820AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP |
| MT90820AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820AP1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel |
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