
MT90820
CMOS
4
40
13
WFPS
Wide Frame Pulse Select (Input):
When 1, enables the wide frame pulse (WFP)
Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode.
41 -
48
14-21
A0 - A7
Address 0 - 7 (Input):
When non-multiplexed CPU bus operation is selected,
these lines provide the A0 - A7 address lines to the internal memories.
49
22
DS/RD
Data Strobe / Read (Input):
For multiplexed bus operation, this input is DS. This
active high DS input works in conjunction with CS to enable the read and write
operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active low
input works in conjunction with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This active low input sets the data
bus lines (AD0-AD7, D8-D15) as outputs.
50
23
R/W / WR
Read/Write / Write (Input):
In the cases of Motorola non-multiplexed and
multiplexed bus operations, this input is R/W. This input controls the direction of
the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access.
For multiplexed bus operation, this input is WR. This active low input is used with
RD to control the data bus (AD0 - 7) lines as inputs.
51
24
CS
Chip Select (Input):
Active low input used by a microprocessor to activate the
microprocessor port of MT90820.
52
25
AS/ALE
Address Strobe or Latch Enable (Input):
This input is used if multiplexed bus
operation is selected via the IM input pin. For Motorola non-multiplexed bus
operation, connect this pin to ground. This pin is pulled low by an internal
pull-down when not driven.
53
26
IM
CPU Interface Mode (input):
When IM is high, the microprocessor port is in the
multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed
mode. This pin is pulled low by an internal pull-down when not driven.
55 -
62
32-39
AD0 - 7
Address/Data Bus 0 to 7 (Bidirectional):
These pins are the eight least
significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
65 -
72
42-49
D8 - 15
Data Bus 8-15 (Bidirectional):
These pins are the eight most significant data
bits of the microprocessor port.
73
50
DTA
Data Transfer Acknowledgement (Active Low Output):
Indicates that a data
bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then
tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up
resistor is required to hold a HIGH level when the pin is tri-stated.
74
55
CSTo
Control Output (Output).
This is a 4.096, 8.192 or 16.384Mb/s output containing
512, 1024 or 2048 bits per frame respectively. The level of each bit is determined
by the CSTo bit in the connection memory. See External Drive Control Section.
76
57
ODE
Output Drive Enable (Input):
This is the output enable control for the STo0 to
STo15 serial outputs. When ODE input is low and the OSB bit of the IMS register
is low, STo0-15 are in a high impedance state. If this input is high, the STo0-15
output drivers are enabled. However, each channel may still be put into a high
impedance state by using the per channel control bit in the connection memory.
77 -
84
58-65
STo0 - 7
Data Stream Output 0 to 7 (Three-state Outputs):
Serial data Output stream.
These streams have selectable data rates of 2.048, 4.096 or 8.192Mb/s.
Pin Description
Pin #
Name
Description
84
PLCC
100
MQFP