參數(shù)資料
型號(hào)： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁(yè)數(shù)： 85/120頁(yè)
文件大?。?/td> 362K
代理商： MT9074
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Advance Information
MT9074
85
Bit
Name
Functional Description
7
RSLIP
Receive Slip
. A change of state (i.e.,
1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.
6
RSLPD
Receive Slip Direction
. If one,
indicates that the last received frame
slip resulted in a repeated frame, i.e.,
system clock is faster than network
clock. If zero, indicates that the last
received frame slip resulted in a lost
frame, i.e., system clock is slower than
network clock. Updated on an RSLIP
occurrence basis.
5
RXFR
M
Receive Frame Delay.
The most
significant bit of the Receive Slip
Buffer Phase Status Word. If zero, the
delay through the receive elastic buffer
is greater than one frame in length; if
one, the delay through the receive
elastic buffer is less than one frame in
length.
4
AUXP
Auxiliary Pattern
. This bit will go high
when a continuous 101010... bit
stream (Auxiliary Pattern) is received
on the PCM 30 link for a period of at
least 512 bits. If zero, auxiliary pattern
is not being received. This pattern will
be decoded in the presence of a bit
error rate of as much as 10-3.
3
CEFS
Consecutively
Alignment Signal.
This bit goes high
when the last two frame alignment
signals were received in error. This bit
will be low when at least one of the last
two frame alignment signals is without
error.
Errored
Frame
2-0
- - -
Unused
.
Table 106 - Most Significant Phase Status Word
(Page 3, Address 13H) (E1)
Bit
Name
Functional Description
7 - 3 RxTS4 - 0
Receive Time Slot
. A five bit
counter that indicates the number
of time slots between the receive
elastic buffer internal write frame
boundary and the ST-BUS read
frame boundary. The count is
updated every 250 uS.
2 - 0 RxBC2 - 0
Receive Bit Count
. A three bit
counter that indicates the number
of STBUS bit times there are
between the receive elastic buffer
internal write frame boundary and
the ST-BUS read frame boundary.
The count is updated every 250
uS.
Table 107 - Least Significant Phase Status Word
(Page 3, Address 14H) (E1)
Bit
Name
Functional Description
7
RIU0
Receive International Use Zero
.
This is the bit which is received on
the PCM 30 2048 kbit/sec. link in bit
position one of the frame alignment
signal. It is used for the CRC-4
remainder or for international use.
6-0
RFA2-8
Receive Frame Alignment Signal
Bits 2 to 8
. These bit are received on
the PCM 30 2048 kbit/sec. link in bit
positions two to eight of frame
alignment signal. These bits form the
frame alignment signal and should
be 0011011.
Table 108 - Receive Frame Alignment Signal
(Page 3, Address 15H) (E1)
相關(guān)PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074AL 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
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