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參數(shù)資料
| 型號： | MT9074 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器) |
| 中文描述： | T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器） |
| 文件頁數(shù)： | 68/120頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MT9074 |
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MT9074
Advance Information
68
Per Channel Receive Signalling (T1 and E1 mode) (Pages 9 and 0AH)
Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive
Signalling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 76 illustrates the mapping
between the addresses of these pages and the DS1 channel numbers. Table 77 describes bit allocation within
each of these registers.
Page 9 Address:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Equivalent DS1
channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Page A Address:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Equivalent DS1
channel
17
18
19
20
21
22
23
24
x
x
x
x
x
x
x
x
Table 76 - Page 9, A Address Mapping to DS1 Channels (T1)
Bit
Name
Functional Description
7 - 4
- - -
Unused
3
A(n)
Receive Signalling Bits A for Channel n
. These bits are extracted from bit
position 8 of every channel in received frame 6 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
3
B(n)
Receive Signalling Bits B for Channel n
. These bits are extracted from bit
position 8 of every channel in received frame 12 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.
2
C(n)
Receive Signalling Bits C for Channel n
. These bits are extracted from bit
position 8 of every channel in received frame 18 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.
0
D(n)
Receive Signalling Bits D for Channel n
. These bits are extracted from bit
position 8 of every channel in received frame 24 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.
Table 77 - Receive Channel Associated Signalling (Pages 9 and A) (T1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9075B | E1 Single Chip Transceiver |
| MT9075B | E1 Single Chip Transceiver(E1單片收發(fā)器) |
| MT9075 | E1 Single Chip Transceiver |
| MT9075A | E1 Single Chip Transceiver |
| MT9075AL | E1 Single Chip Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9074_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074AL | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
| MT9074AL1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
| MT9074AP | 制造商:Microsemi Corporation 功能描述: |
| MT9074AP1 | 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC |
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