參數(shù)資料
型號(hào)： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁數(shù)： 75/120頁
文件大?。?/td> 362K
代理商： MT9074
Advance Information
MT9074
75
Bit
Name
Functional Description
7
RST
Reset
. When this bit is changed
from zero to one the device will
reset to its default mode. See the
Reset Operation section for the
default settings.
6
SPND
Suspend Interrupts
. If one, the
IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance
state and all interrupts will be
ignored. If zero, the IRQ output will
function normally.
5
INTA
Interrupt Acknowledge
. A zero-to-
one or one-to-zero transition will
clear any pending interrupt and
make IRQ high impedance.
4
CNTCLR
Counter Clear
. If one, all status
counters are cleared and held low.
Zero for normal operation.
3
SAMPLE
One Second Sample
. Setting this
bit causes the error counters
(change of frame alignment, loss of
frame alignment, bpv errors, crc
errors,
severely
events and multiframes out of sync)
to be updated on one second
intervals coincident with the one
second
timer
address 12H bit 7).
errored
frame
(status
page
3
2
EXTOSC
External Oscillator Select
. Setting
this bit connects the pin OSC1 to a
TTL compatible input. This allows
for a system design employing a
TTL output oscillator as a 20.000
Mhz reference clock.
1
RSV
Reserved.
Must be kept at 0 for
normal operation.
0
- - -
Unused.
Table 89 - Signalling Control Word (E1)
(Page 1, Address 1AH)
Bit
Name
Functional Description
7
SYNIM
Synchronization
Mask.
When unmasked (SYNI=1)
an interrupt is initiated whenever
change of state of basic frame
synchronization condition exists.
If 1 - unmasked, 0 - masked.
Interrupt
6
MFSYIM
Multiframe
Interrupt Mask
. When unmasked
(MFSYI=1),
an
initiated whenever a change of
state of multiframe synchro-
nization is lost. If 1 - unmasked, 0
- masked.
Synchronization
interrupt
is
5
CSYNIM
CRC-4
Synchronization
Mask
.
(CSYNI=1),
initiated whenever a change of
state of CRC-4 multiframe
synchronization exists. If 1 -
unmasked, 0 - masked.
Multiframe
Interrupt
unmasked
interrupt
When
an
is
4
AISIM
Alarm
Interrupt Mask.
When unmasked
(AISI=1) a change of state of
received AIS will initiate an
interrupt. If 1 - unmasked, 0 -
masked.
Indication
Signal
3
LOSIM
Loss of Signal Interrupt Mask
.
When unmasked this interrupt bit
goes high whenever a change of
state of loss of signal (either
analog - received signal 20 or 40
dB below nominal or digital - 192
consecutive
0’s
condition exists. If 1 - unmasked,
0 - masked.
received)
2
CEFIM
Consecutively Errored FASs
Interrupt Mask
. When unmasked
an interrupt is initiated when two
consecutive
errored
alignment signals are received. If
1 - unmasked, 0 - masked.
frame
Table 90 - Interrupt Mask Word Zero (E1)
(Page 1, Address 1BH)
相關(guān)PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
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MT9074AP 制造商:Microsemi Corporation 功能描述:
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