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| 型號： | MT8980 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 80K |
| 代理商： | MT8980 |
Application Note
MSAN-123
A-113
The minimum delays from the time a channel enters
the MT8980 on an ST-BUS input to the time that the
information in the channel can be extracted from the
Data Memory are given in Table 3. They are
measured from the end of the input channel’s
timeslot to the rising edge of DS. The rising edge of
DS corresponds to the earliest point DS may be
activated to access the first available microprocessor
window from which the information will be visible
(see SECTION 5.0).
If the byte of Data Memory that corresponds to the
desired channel is accessed earlier than the
minimum delay dictates, then the contents of the
byte read by the microprocessor will be the
information that the channel contained on the
previous frame. Conversely, if slightly less than one
frame of delay is added to the minimum delay (508
C4i clock cycles rather the 512 that make up a
frame) the contents of the byte will be the information
contained in the channel in the frame following the
desired frame.
5.0 Microprocessor Accesses
In the MT8980 data sheet, a parameter is specified
(t
AKD
) for the maximum time taken to return Data
Acknowledge after DS goes high. There are two
values for this time, one labelled fast, and one
labelled slow. The fast t
AKD
applies to writes to the
Control Register. The Control Register can accept
data very quickly, and will not cause wait states for
most microprocessors. Reading the Control Register
and reading or writing to any other part of the
MT8980 will receive a slower response (t
AKD
slow).
Slow microprocessor bus transfers occur because
the MT8980 only allocates discrete access windows
for the slow transfers. Microprocessor access
windows occur every four C4i clock cycles during a
frame, relative to the frame boundary. Figure 6 and
Figure 7 show the relationship between micro-
processor access windows, C4i, DS and the return of
DTA.
DTA goes low one half
a microprocessor access window in which the set up
requirements for DS are met and the operation is a
write. If the operation is a read and DS setup is met,
DTA goes low one C4i clock cycle after the access
window. DS must be set up three C4i cycles ahead of
the falling edge of every microprocessor window
cycle to meet minimum set up requirements for
accessing a window.
If the controlling microprocessor can determine
where the falling edge of every fourth C4i cycle in a
frame occurs, it may use this as a signal to continue
C4i cycle after
on to the next bus cycle rather than wait for DTA to
go low. DTA is a signal provided only to tell the
microprocessor that the MT8980 is ready to finish
the current bus cycle. DS could be removed between
the end of the microprocessor access window
and the point where DTA would normally go low and
the transfer of information would still complete
successfully. In such a situation, DTA would not
go low for that particular bus cycle.
Figure 7 shows the two ways in which DTA can be
returned in response to a microprocessor
access. The possible transitions of DTA and DS
are dotted lines, not solid, because there are several
options. If DS goes low at the first transition point,
DTA does not go low. If DS is held high, the two
places that a transition on DTA can occur are shown.
6.0 External Control Using CSTo
CSTo is a 2.048 Mbit/s output which is, like the ST-
BUS streams, divided into frames that are 256 bits
long. Each bit is controlled by one of the 256
CMH
b
1’s. If a CMH
b
1 is a logical ‘1’, the
corresponding bit on CSTo is a high. If the CMH
b
1 is
a logical ‘0’, the corresponding bit on CSTo is a low.
Unlike the other ST-BUS outputs, though, CSTo
cannot be placed into a high impedance state.
The CMH
b
1’s of locations that are related by channel
timeslot are output sequentially. As an example,
there are eight CMH
b
1’s corresponding to channel
zero, one bit for each stream. These bits are output
sequentially on CSTo in the following order:
a) CMH
b
1 for STo0 Channel 0
b) CMH
b
1 for STo1 Channel 0
c) CMH
b
1 for STo2 Channel 0
d) CMH
b
1 for STo3 Channel 0
e) CMH
b
1 for STo4 Channel 0
f) CMH
b
1 for STo5 Channel 0
g) CMH
b
1 for STo6 Channel 0
h) CMH
b
1 for STo7 Channel 0
The eight CSTo bits that correspond to a channel
position are output in the timeslot preceding the
actual channel position. The reason for this is that
CSTo bits are designed to perform external control
functions on the individual channels they correspond
to.
One control function these bits may perform is to
control loop back circuitry for individual channels. If
a CSTo bit is set, the loopback circuitry could drive
an MT8980 input with the information from the
corresponding output channel. This function would
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PDF描述 |
|---|---|
| MT8982 | ISO-CMOS ST-BUS⑩ FAMILY Small Digital Switch (MiniDX) |
| MT8982AC | ISO-CMOS ST-BUS⑩ FAMILY Small Digital Switch (MiniDX) |
| MT8982AE | ISO-CMOS ST-BUS⑩ FAMILY Small Digital Switch (MiniDX) |
| MT8982AN | ISO-CMOS ST-BUS⑩ FAMILY Small Digital Switch (MiniDX) |
| MT8982AS | ISO-CMOS ST-BUS⑩ FAMILY Small Digital Switch (MiniDX) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8980D | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:ISO-CMOS ST-BUS Family Digital Switch |
| MT8980D-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY Digital Switch |
| MT8980DE | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 5V 40PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256 5V 40PDIP - Rail/Tube |
| MT8980DE1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 5V 40PDIP - Rail/Tube 制造商:Microsemi Corporation 功能描述:PB FREE DIGITAL SWITCH 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256 5V 40PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DIGITAL SWITCH |
| MT8980DP | 制造商:Mitel Networks Corporation 功能描述: 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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