
Application Note
MSAN-123
A-107
Information must be placed on the ST-BUS stream
and removed from it synchronously. In most
applications, information is placed onto the ST-BUS
or received from it in one particular channel timeslot
(more than one channel may be used for more
bandwidth). Any device interfaced to the ST-BUS
must accept a clock signal for bit timing and a
framing signal for synchronization with the frame
boundaries. There are several types of clock signals
and frame synchronization signals (framing pulses)
defined for the ST-BUS. These signals are described
in
the
ST-BUS
specification
Semiconductor Data Book.
in
the
Mitel
3.0 Architecture of MT8980
The MT8980 architecture is illustrated in Figure 1.
3.1 ST-BUS Interface to the MT8980/81
The clock input of the MT8980/81 is called C4i and
its frequency (4.096 MHz) is twice the data rate.
The frame pulse is the F0i signal. See Figure 2 for
the timing relationship between C4i, F0i and the bits
and channels of the ST-BUS.
The ST-BUS outputs of the MT8980/81 derive their
output information from two sources: from the ST-
BUS streams input to the MT8980/81 and/or from the
microprocessor controlling the MT8980/81. The
MT8980/81 is also designed to allow the controlling
microprocessor to read the information on the input
ST-BUS channels.
The MT8980/81 has two modes of operation to
accommodate the choice of information sources:
Switching mode and Message mode. Switching
mode allows the information contained in each
output channel to be chosen from any of the input
channels in a non-blocking fashion. An advantage of
having the output specify the source is that more
than one output, all outputs in fact, can have the
same source. This is advantageous for broadcasting
messages or generating resource channels (e.g.,
dial tone can be input in one channel but output in
many). Message mode allows information to be
written through the microprocessor port onto the
output channels. This information will not change
until rewritten. The information on the input channels
can be read by the microprocessor no matter what
mode the device is in.
The major difference between the MT8980 and the
MT8981 is the number of 32 channel streams which
each can handle. The MT8980 has eight ST-BUS
inputs and eight ST-BUS outputs (256 channels in,
256 channels out). The MT8981 has four ST-BUS
inputs and four ST-BUS outputs (128 channels in,
128 channels out). Essentially, the MT8980 is a 256
crosspoint digital switch, and the MT8981 is a 128
crosspoint digital switch. Also, the MT8981 does not
have a CSTo output (see Section 6.0). The basic
similarities between the two devices allow both to be
referred to as the MT8980, unless explicit reference
to the MT8981 is needed.
3.2 Microprocessor Interface
The microprocessor port consists of a data bus for
information transfer, an address bus, a chip enable,
two signals for synchronizing microprocessor bus
transfers, and a transfer direction control signal. The
data bus is eight bits wide and carries control
information for the MT8980 from the microprocessor.
The six address bits, A0-A5, help determine which of
the individual locations within the MT8980 are
accessed.
The Select signal (CS) is the chip enable. If CS is
high, no access to the MT8980 is possible. Normally,
when DS is brought low, most systems remove the
CS signal. This is not mandatory, as the MT8980 will
not drive the data bus or receive information from the
data bus unless DS is high. The Data Strobe signal
(DS) and the Data Acknowledge signal (DTA)
perform transfer synchronization. At the rising edge
of DS, all other control information must be valid. On
the falling edge of DS, data from the microprocessor
or data from the MT8980 is valid. DS is usually not
brought low until after the MT8980 brings the
DTA signal low, which occurs when the MT8980 is
ready to accept or provide data. Once DS is low, the
MT8980 brings DTA high, terminating the bus cycle.
The Read/Write signal (R/W) determines the
direction of information flow. When the signal is high,
information can be read from the MT8980 by the
microprocessor. When R/W is low, data from the
microprocessor may be written to the MT8980.
3.3 Internal structure
There are four major functional blocks inside the
MT8980. These blocks are the Data Memory, the
Connection Memory High, the Connection Memory
Low and the Control Register. Data Memory is
related to the input ST-BUS streams; Connection
Memory High and Connection Memory Low are
related to the output ST-BUS streams. The Control
Register performs block addressing functions and
overall mode determination.
The Data Memory is where information is stored as it
comes in from the ST-BUS inputs. The loading of
information into Data Memory from the inputs is
automatic (Data Memory may not be written into