
MSAN-123
Application Note
A-112
stream it is output on. Figure 4 shows the delay of
data through the MT8980 for information switched
one channel forward. Figure 5 shows the delay of
data through the MT8980 for information switched
three channels forward. Note that in Figure 4 the
input data is not output until one frame later, but in
Figure 5 the delay is minimal.
The maximum delay is one frame
period (approximately 125 microseconds or 512
C4i clock cycles) plus two channels. This is the
delay resulting if a switch two channels forward does
not meet the input/output stream requirements of
Table 1. The minimum delay achievable is two
channels. This is the delay resulting if the
requirements of Table 1 are met.
4.2 Message Mode
In Message mode, there are two delays to contend
with. The first delay is the delay between receiving
information on the ST-BUS and reading it through the
microprocessor port (this delay is not actually
constrained to Message mode, as an input channel
may be read by the microprocessor independent of
any channels being in Switching mode or Message
Mode. The other delay is the delay between writing
information into Connection Memory Low and
transmitting the information on the ST-BUS output.
As with Switching mode, information destined for a
particular timeslot on the ST-BUS is sent to the
output stream queue during the preceding timeslot.
The time during the preceding channel that this
occurs is dependent on the stream. The sequence in
which the information destined for an output channel
is sent to each stream is: STo0, STo1, STo2, STo3,
STo4, STo5, STo6, STo7.
To use this information about output sequencing and
internal information movement, the microprocessor
must synchronize transfers with ST-BUS timing. If
the microprocessor transfer is not made before a
channel’s information is sent to the queue, the newly
transferred information will not be output until the
next frame.
To ensure that a particular channel on a particular
stream may be written to without a one frame delay,
a minimum set up time for the write in question must
be respected. This set up time is relative to the start
of the output channel’s timeslot. Table 2 shows the
minimum set up times for the different ST-BUS
streams (set up times are expressed in multiples
of t
CLK
, the period of the C4i clock). There can also
be a maximum set up time, if writing information one
frame early to a particular channel on a particular
stream is undesirable. The maximum set up time is
merely the minimum set up time plus one frame.
Figure 7 - DS Setup Time and DTA Return Relative to C4i and Microprocessor Access Window
Figure 6 - Position of Microprocessor Access Windows Relative to ST-BUS Channel and C4i Timing
C4i
DTA
DS
DS set up time
Writes
Reads
Microprocessor access windows
Bit 7
Bit 6
Bit 5
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
Bit 7
Bit 6
Bit 5
C4i
ST-BUS
Bit
timing
Channel N
Microprocessor access window