參數(shù)資料
型號: MT8980
廠商: Mitel Networks Corporation
英文描述: ()
中文描述: ()
文件頁數(shù): 5/11頁
文件大小: 80K
代理商: MT8980
Application Note
MSAN-123
A-109
mode) or be output in the associated ST-BUS output
channel (Message mode). When the microprocessor
is writing to or reading from Connection Memory
Low, the address of the location being written to is
formed by CR
b
2, CR
b
1, CR
b
0, A4, A3, A2, A1, and
A0. Either the Message mode or Switching mode
function of the Connection Memory contents is
performed automatically once per frame.
Connection
microprocessor like Connection Memory Low did, in
terms of size of the memory array, method of
addressing and being able to be both read from and
written to. Each byte of the Connection Memory
High is associated with the same output channel as
the related byte in the Connection Memory Low.
Memory
High
appears
to
the
Only three bits of the Connection Memory High are
useful, bits CMH
b
2, CMH
b
1 and CMH
b
0. The other
five bits are read as zeroes, and are not changeable.
When CMH
b
0 is a logical ‘0’ the output channel
associated with the Connection Memory High
location is placed into a high impedance state.
When CMH
b
0 is set to a logical ‘1’, the output
channel driver is turned on and information from
either Data Memory (switched mode) or Connection
Memory Low (Message mode) is placed on the
output. CMH
b
1 controls the state of the bit on the
CSTo output that is associated with that particular
Connection Memory High location and channel. This
bit is not used in the MT8981. CMH
b
2 is the
channel’s mode control bit. When CMH
b
2 is a logical
‘0’, the associated output channel is placed into
Switching mode and the contents of the Data
Memory location addressed by Connection Memory
Low are output on the channel. When CMH
b
2 is a
logical ‘1’, the output channel is in Message mode
and the contents of Connection Memory Low are
placed on the output channel.
The Control Register is an eight bit register which
may be written to or read from the microprocessor
port. This register is accessed when A5 is low.
When A5 is high, one of the other memory blocks,
Data
Memory,
Connection
Connection Memory High, is visible to the
microprocessor port. CR
b
4 and CR
b
3 determine
which of the memory blocks is being accessed and
CR
b
2, CR
b
1 and CR
b
0 determine which portion of
the selected memory block is visible. Each memory
block portion selected by CR
b
2-0 is 32 bytes long,
corresponding to the 32 channels of one of the ST-
BUS streams. The state of A4-A0 determines which
byte in a 32 byte segment is accessed by the
microprocessor at any one time. Figure 3 shows the
relationship between CR
b
4-0, A5-A0, and channel
accesses in the MT8980.
Memory
Low
or
CR
b
6 is an overall Message mode bit. This bit can
override the setting of the CMH
b
2 and the CMH
b
0 of
an output channel. If CR
b
6 is set to a logical ‘1’, all
output channels are in Message mode and the
CMH
b
0 and the CMH
b
2 of each channel has no
effect. If CR
b
6 is low, the Connection Memory High
bits determine the mode of their respective channels
(Switching or Message) and whether the channel is
in a high impedance state or not.
CR
b
7 is called the Split Mode bit and is an override
of CR
b
4 and CR
b
3. If CR
b
7 is set to a logical ‘1’, the
device is in split mode. All microprocessor writes to
the MT8980 in Split mode are to the Connection
Memory Low. All microprocessor reads of the
MT8980 in split mode are from Data Memory. If
CR
b
7 is a logical ‘0’, memory block selection is
determined by CR
b
4 and CR
b
3.
The last bit in the Control Register, CR
b
5, is unused.
Also, when using the MT8981, CR
b
2 is unused. It is
also important to note that CRb4 and CRb3 must
never be set to ‘00’.
3.4 Programming Examples
The way the control register, the memory blocks and
the external address bits work together is clarified
with several examples.
In the first example, the operation of reading
information contained in Channel 5 of Input Stream 2
(STi2)
through
the
microprocessor
examined. To read ST-BUS input information, the
microprocessor must read the Data Memory. Data
Memory may be specified in the Control Register by
either setting the Split Mode bit, CR
b
7, to a logical
‘1’, or by setting CR
b
4 and CR
b
3 to the binary state
‘01’. To access the portion of Data Memory
corresponding to STi2, CR
b
2, CR
b
1 and CR
b
0 must
be set to ‘010’. CR
b
6 and CR
b
5 have no effect on
this example. Once the Control Register bits are set
up in this manner, the microprocessor can read the
information contained in any of the channels of STi2
by keeping A5 high and using A4-A0 to determine
which channel is to be read. To access Channel 5,
A4-A0 must be set to ‘00101’.
port
is
Example two consists of switching Channel 31 on
STi0 to Channel 1 on Output Stream 7 (STo7). In
this case, the locations corresponding to Channel 1
on STo7 in the two Connection Memories have to be
accessed. Connection Memory Low must contain
the Data Memory address of the source channel.
Connection Memory High specifies the mode of
Channel 1 on STo7 and whether it is in a high
impedance state or not. To access Connection
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