參數(shù)資料
型號(hào)： MT58L64V32P
廠商： Micron Technology, Inc.
英文描述： 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 64K的× 32，流水線，SCD的SyncBurst的SRAM（處理器，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 487K
代理商： MT58L64V32P
9
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
9B
x32/x36
9B
SYMBOL
ADSP#
TYPE
Input
DESCRIPTION
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this
input selects “l(fā)inear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQa’s;
Output Byte “b” is associated with DQb’s. For the x32 and x36 versions,
Byte “a” is associated with DQa’s; Byte “b” is associated with DQb's;
Byte “c” is associated with DQc’s; Byte “d” is associated with DQd’s.
Input data must meet setup and hold times around the rising edge
of CLK.
8A
8A
ADSC#
Input
1R
1R
MODE
(LB0#)
Input
(a)
10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b)
1J, 1K,
1L, 1M, 2D,
2E, 2F, 2G
(a)
10J, 10K,
DQa
(b)
10D, 10E,
10F, 10G, 11D,
11E, 11F, 11G
(c)
1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d)
1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11N
11C
1C
1N
DQb
DQc
DQd
11C
1N
–
–
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply:
See DC Electrical Characteristics and Operating
Conditions for range.
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
(continued)
相關(guān)PDF資料
PDF描述
MT58L64L36P 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L64V36P 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
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MT58L128L32P1 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L64V32PT-6 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V
MT58L64V32PT-7.5 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 4ns 100-Pin TQFP
MT58L64V32PT-7.5 IT 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC IND TEMP T
MT58L64V32PT-7.5 TR 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V
MT58L64V36F 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
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