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參數(shù)資料
| 型號(hào)： | MT58L64V32P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 64K的× 32，流水線，SCD的SyncBurst的SRAM（處理器，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 20/25頁(yè) |
| 文件大?。?/td> | 487K |
| 代理商： | MT58L64V32P |
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20
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
ADV#
suspends
burst.
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
(NOTE 4)
Burst continued with
new base address.
DON’T CARE
UNDEFINED
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
-5
-6
-7.5
-10
SYMBOL
t
AS
t
ADSS
t
AAS
t
WS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
CEH
MIN MAX MIN MAX MIN MAX MIN MAX
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
2.2
2.2
2.2
2.2
2.2
0.5
0.5
0.5
0.5
0.5
READ TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
MIN MAX MIN MAX MIN MAX MIN MAX
5.0
6.0
200
166
1.6
1.7
1.6
1.7
3.5
3.5
1.0
1.5
0
1.5
3.5
3.5
3.5
3.5
0
0
3.0
3.5
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
10
133
100
1.9
1.9
3.2
3.2
4.0
5.0
1.5
1.5
1.5
1.5
4.0
4.0
5.0
5.0
0
0
4.0
4.5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L64L36P | 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L64V36P | 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L32D1 | 128K x 32，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L36D1 | 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L32P1 | 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64V32PT-6 | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L64V32PT-7.5 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 4ns 100-Pin TQFP |
| MT58L64V32PT-7.5 IT | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC IND TEMP T |
| MT58L64V32PT-7.5 TR | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L64V36F | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
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