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參數(shù)資料
| 型號(hào)： | MT58L32L32F |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 32K x 32， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| 中文描述： | 32K的× 32，3.3V的I / O的流量通過SyncBurst的SRAM（1兆，3.3V的輸入/輸出，流通式同步脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 327K |
| 代理商： | MT58L32L32F |
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM
MT58L64L18F.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
11
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
NOTE:
1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. This parameter is measured with output loading shown in Figure 2.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “ Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “ Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE
cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0oC
≤
T
A
≤
+70oC; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V)
-7.5
-8.5
-10
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Byte write enables
(BWa#-BWd#, GW#, BWE#)
Data-in
Chip enable (CE#)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Byte write enables
(BWa#-BWd#, GW#, BWE#)
Data-in
Chip enable (CE#)
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
t
KC
f
KF
t
KH
t
KL
8.8
10.0
15
ns
113
100
66
MHz
ns
ns
1.9
1.9
1.9
1.9
4.0
4.0
2
2
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
7.5
8.5
10.0
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
3.0
4.0
3.0
4.0
3
3, 4, 5, 6
3, 4, 5, 6
7
3, 4, 5, 6
3, 4, 5, 6
4.2
4.2
5.0
5.0
5.0
5.0
0
0
0
4.2
5.0
5.0
t
AS
t
ADSS
t
AAS
t
WS
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
DS
t
CES
2.0
2.0
2.0
2.0
2.5
2.5
ns
ns
8, 9
8, 9
t
AH
t
ADSH
t
AAH
t
WH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
DH
t
CEH
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
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| MT58L32L32FT-10 | 制造商:Cypress Semiconductor 功能描述:32KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L32L32FT-10 TR | 制造商:Cypress Semiconductor 功能描述:32KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L32L32FT-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L32L32FT-8.5 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 1M-Bit 32K x 32 8.5ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L32L32FT-8.5 TR | 制造商:Cypress Semiconductor 功能描述:32KX32 SRAM PLASTIC TQFP 3.3V |
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