參數(shù)資料
型號(hào)： MT58L32L36P
廠商： Micron Technology, Inc.
英文描述： 32K x 36, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 32K的× 36，3.3V的I / O的流水線，SCD的SyncBurst的SRAM（1兆，3.3V的輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 1/17頁(yè)
文件大?。?/td> 329K
代理商： MT58L32L36P
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
MT58L64L18P.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
1
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
FEATURES
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V +0.3V/-0.165V isolated output
buffer supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Single-cycle deselect (Pentium
BSRAM-
compatible)
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP for high density, high speed
Low capacitive bus loading
x18, x32 and x36 options available
OPTIONS
Timing (Access/Cycle/MHz)
3.5ns/6.0ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
Configurations
64K x 18
32K x 32
32K x 36
Package
100-pin TQFP
Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
MARKING
-6
-7.5
-10
MT58L64L18P
MT58L32L32P
MT58L32L36P
T
None
IT
Part Number Example:
MT58L64L18PT-10 IT
MT58L64L18P, MT58L32L32P,
MT58L32L36P
3.3V V
DD
, 3.3V I/O, Pipelined, Single-
Cycle Deselect
through registers controlled by a positive-edge-trig-
gered single clock input (CLK). The synchronous inputs
include all addresses, all data inputs, active LOW chip
enable (CE#), two additional chip enables for easy
depth expansion (CE2, CE2#), burst control inputs
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and
global write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode pin (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
GENERAL DESCRIPTION
The Micron
SyncBurst
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
The MT58L64L18P and MT58L32L32/36P 1Mb
SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM
core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass
*JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP*
1Mb SYNCBURST
SRAM
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