參數(shù)資料
型號(hào): MT58L256L18P1
廠商: Micron Technology, Inc.
英文描述: 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 256 × 18,流水線,SCD的SyncBurst的SRAM(4MB,在流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 18/28頁(yè)
文件大?。?/td> 445K
代理商: MT58L256L18P1
18
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
Q
50
V = 1.5V
Z = 50
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
LOAD DERATING CURVES
Micron 256K x 18, 128K x 32, and 128K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
3.3V I/O AC TEST CONDITIONS
Input pulse levels ................. V
IH
= (V
DD
/2.2) + 1.5V
....................V
IL
= (V
DD
/2.2) - 1.5V
Input rise and fall times..................................... 1ns
Input timing reference levels..................... V
DD
/2.2
Output reference levels ............................V
DD
Q/2.2
Output load ............................. See Figures 1 and 2
Q
50
V = 1.25V
Z = 50
Figure 3
Q
225
225
5pF
+2.5V
Figure 4
2.5V I/O AC TEST CONDITIONS
Input pulse levels ............. V
IH
= (V
DD
/2.64) + 1.25V
................V
IL
= (V
DD
/2.64) - 1.25V
Input rise and fall times..................................... 1ns
Input timing reference levels................... V
DD
/2.64
Output reference levels ...............................V
DD
Q/2
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
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