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參數(shù)資料
| 型號(hào)： | MT58L256L18P1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 256 × 18，流水線，SCD的SyncBurst的SRAM（4MB，在流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大小： | 445K |
| 代理商： | MT58L256L18P1 |
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4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
TRUTH TABLE
OPERATION
ADDRESS
USED
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE# CE2# CE2
H
X
L
X
L
H
L
X
L
H
X
X
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
X
H
X
X
X
H
X
X
X
X
X
H
X
H
X
X
X
H
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP# ADSC# ADV# WRITE# OE#
X
L
L
X
L
X
H
L
H
L
X
X
L
X
L
X
H
L
H
L
H
L
H
H
H
H
X
H
X
H
H
H
X
H
H
H
H
H
H
H
X
H
H
X
H
H
H
H
H
X
H
H
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “ Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s
and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
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| MT58L256L18P1T-10 | 制造商:Cypress Semiconductor 功能描述:256KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L256L18P1T-10 IT | 制造商:Cypress Semiconductor 功能描述: |
| MT58L256L18P1T10A | 制造商:Micron Technology Inc 功能描述: |
| MT58L256L18P1T-5 | 制造商:Cypress Semiconductor 功能描述:256KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L256L18P1T-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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