參數(shù)資料
型號(hào)： MT58L256L18P1
廠商： Micron Technology, Inc.
英文描述： 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 256 × 18，流水線，SCD的SyncBurst的SRAM（4MB，在流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 445K
代理商： MT58L256L18P1
14
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C
￡
T
A
￡
+70°C; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
CONDITIONS
SYMBOL
V
IH
V
IL
IL
I
IL
O
MIN
2.0
-0.3
-1.0
-1.0
MAX
V
DD
+ 0.3
0.8
1.0
1.0
UNITS
V
V
μA
μA
NOTES
1, 2
1, 2
3
0V
￡
V
IN
￡
V
DD
Output(s) disabled,
0V
￡
V
IN
￡
V
DD
I
OH
= -4.0mA
I
OL
= 8.0mA
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
V
OH
V
OL
V
DD
V
DD
Q
2.4
–
3.135
3.135
–
V
V
V
V
1, 4
1, 4
1
1, 5
0.4
3.6
3.6
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
............................... -0.5V to +4.6V
Voltage on V
DD
Q Supply
Relative to V
SS
............................... -0.5V to +4.6V
V
IN
-0.5V to V
DD
Q + 0.5V
Storage Temperature (plastic) ............ -55°C to +150°C
Junction Temperature**................................... +150°C
Short Circuit Output Current ...........................100mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum junction temperature depends upon pack-
age type, cycle time, loading, ambient temperature and
airflow. See Micron Technical Note TN-05-14 for more
information.
NOTE:
1. All voltages referenced to V
SS
(GND).
2. Overshoot:
V
IH
￡
+4.6V for t
￡
t
KC/2 for I
￡
20mA
Undershoot:
V
IL
3
-0.7V for t
￡
t
KC/2 for I
￡
20mA
Power-up:
V
IH
￡
+3.6V and V
DD
￡
3.135V for t
￡
200ms
3. MODE pin has an internal pull-up, and input leakage = ±10μA.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be connected together, for 3.3V I/O operation only.
6. This parameter is sampled.
7. Preliminary package data.
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
T
A
= 25°C; f = 1 MHz;
V
DD
= 3.3V
SYMBOL
C
I
C
O
C
A
C
CK
TYP
3
4
3
3
MAX
4
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
6
6
6
6
FBGA CAPACITANCE
DESCRIPTION
Address/Control Input Capacitance
Output Capacitance (Q)
Clock Capacitance
CONDITIONS
SYMBOL
C
I
C
O
C
CK
TYP
2.5
4
2.5
MAX
3.5
5
3.5
UNITS
pF
pF
pF
NOTES
6, 7
6, 7
6, 7
T
A
= 25°C; f = 1 MHz
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