參數(shù)資料
型號(hào)： MT49H32M9CFM-xx
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁(yè)數(shù)： 9/44頁(yè)
文件大小： 1117K
代理商： MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
9
Table 2:
Ball Descriptions
SYMBOL
CK, CK#
TYPE
Input
DESCRIPTION
Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip Select: CS# enables the command decoder when LOW and disables it when HIGH.
When the command decoder is disabled, new commands are ignored, but internal
operations continue.
Command Inputs: Sampled at the positive edge of CK, WE#, and REF# define (together
with CS#) the command to be executed.
Address Inputs: A[0:20] define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET, the address inputs define the register
settings. They are sampled at the rising edge of CK. In the x18 configuration, A[20] is
reserved for address expansion. These expansion addresses can be treated as address
inputs, but they do not affect the operation of the device.
Reserved for future use. This signal is internally connected and can be treated as an
address input.
Reserved for future use. This signal is not connected and may be connected to ground.
Input Data Clock: DKx and DKx# are the differential input data clocks. All input data is
referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. D0–
D17 are referenced to DK0 and DK0#.
Input Data Mask: The DM signal is the input mask signal for WRITE data. Input data is
masked when DM is sampled HIGH, along with the WRITE input data. DM is sampled on
both edges of DK.
Bank Address Inputs: Select to which internal bank a command is being applied.
Data Input: The D signals form the 18-bit input data bus. During WRITE commands, the
data is referenced to both edges of DK.
Data Output: The Q signals form the 18-bit output data bus. During READ commands,
the data is referenced to both edges of QK.
Output Data Clocks: QKx and QKx# are opposite polarity, output data clocks. During
READs, they are free running and edge-aligned with data output from the RLDRAM.
QKx# is ideally 180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–
Q8 and QK1 and QK1# are aligned with Q9–Q17. Consult the RLDRAM II Design Guide
for more details.
Data Valid: The QVLD indicates valid output data. QVLD is edge-aligned with QKx and
QKx#.
IEEE 1149.1 Test Inputs: These balls may be left as No Connects if the JTAG function is
not used in the circuit
IEEE 1149.1 Clock Input: This ball must be tied to V
SS
if the JTAG function is not used in
the circuit.
IEEE 1149.1 Test Output: JTAG output.
External Impedance [25
–60
]: This signal is used to tune the device outputs to the
system data bus impedance. Q output impedance is set to 0.2 x RQ, where RQ is a
resistor from this signal to ground. Connecting ZQ to GND invokes the minimum
impedance mode. Connecting ZQ to V
DD
invokes the maximum impedance mode. Refer
to Figure 10 on page 16 to activate this function.
Input Reference Voltage: Nominally V
DD
Q/2. Provides a reference voltage for the input
buffers.
Power Supply: 2.5V nominal. See Table 19, DC Electrical Characteristics and Operating
Conditions, on page 41 for range.
Power Supply: 1.8V nominal. See Table 19, DC Electrical Characteristics and Operating
Conditions, on page 41 for range.
CS#
Input
WE#, REF#
Input
A[0:20]
Input
A21
–
A22
–
DKx, DKx#
Input
DM
Input
BA[0:2]
D0–D17
Input
Input
Q0–Q17
Output
QKx, QKx#
Output
QVLD
Output
TMS
TDI
TCK
Input
Input
TDO
ZQ
Output
Input/Output
V
REF
Input
V
EXT
Supply
V
DD
Supply
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