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參數(shù)資料
| 型號： | MT49H32M9CFM-xx |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 1117K |
| 代理商： | MT49H32M9CFM-XX |
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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
28
On-Die Termination
On-die termination (ODT) is enabled by setting A9
to “1” during an MRS command. With ODT on, all the
DQs and DM are terminated to V
TT
with a resistance
R
TT
. The command, address, and clock signals are not
terminated. Figure 28 below shows the equivalent cir-
cuit of a
Q driver with ODT. ODTs are dynamically
switched off during READ commands and are
designed to be off prior to the RLDRAM driving the
bus. Similarly, ODTs are designed to switch on after the
RLDRAM has issued the last piece of data. ODT at the
D inputs and DM are always on.
NOTE:
1. All voltages referenced to V
SS
(GND).
2. V
TT
is expected to be set equal to V
REF
and must track
variations in the DC level of V
REF
.
3. The R
TT
value is measured at 70°C T
C
.
Figure 28: On-Die Termination-
Equivalent Circuit
Figure 29: READ Burst with ODT: BL = 2, Configuration 1
NOTE:
A/BA
x
: address A of bank
x
RD: READ
Q
xy
: Data
y
to bank
x
RL: READ latency
Table 9:
On-Die Termination DC
Parameters
DESCRIPTION
SYM
MIN
MAX
UNITS
NOTES
Termination
Voltage
On-Die
Termination
V
TT
0.95
X
V
REF
135
1.05
X
V
REF
165
V
1, 2
R
TT
3
V
TT
R
TT
sw
Driver
Q
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
ADDR
RL = 4
Q
QKx
QKx#
Q0a
Q1a
Q0b
Q1b
Q2a
Q2b
RD
BA
A
BA
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
DON’T CARE
UNDEFINED
ODT
ODT ON
QVLD
ODT OFF
ODT ON
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