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參數(shù)資料
| 型號： | MT49H32M9CFM-xx |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁數(shù)： | 11/44頁 |
| 文件大?。?/td> | 1117K |
| 代理商： | MT49H32M9CFM-XX |
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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
11
NOTE:
1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.
2. Actual refresh is 32ms/8K/8 = 0.488μs.
3. Actual refresh is 32ms/8k = 3.90μs.
Table 5:
Description of Commands
COMMAND
DESCRIPTION
DESEL/NOP
1
The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects
the chip. Use the NOP command to prevent unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected. Output values depend on
command history.
The mode register is set via the address inputs A(17:0). See Figure 10 on page 16 for further
information. The MRS command can only be issued when all banks are idle and no bursts are in
progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within
the bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within
the bank. Input data appearing on the DS is written to the memory array subject to the DM input
logic level appearing coincident with the data. If the DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored (i.e., this part of the data word will not be written).
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a
bank. The command is nonpersistent, so it must be issued each time a refresh is required. The value
on the BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh
controller, effectively making each address bit a “Don’t Care” during the AREF command. The
RLDRAM requires 64K cycles at an average periodic interval of 0.49μs
2
(MAX). To improve
efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic
intervals of 3.9μs
3
.
MRS
READ
WRITE
AREF
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| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT49H32M9CHU-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CHU-33 | 制造商:Micron Technology Inc 功能描述:32MX9 RLDRAM PLASTIC FBGA 1.8V SEPARATE I/O 8 BANKS 1.8V I/O - Trays |
| MT49H32M9CHU-5 | 制造商:Micron Technology Inc 功能描述:32MX9 RLDRAM PLASTIC FBGA 1.8V SEPARATE I/O 8 BANKS 1.8V I/O - Trays |
| MT49H32M9FM-25 | 制造商:Micron Technology Inc 功能描述: |
| MT49H32M9FM-25 TR | 功能描述:IC RLDRAM 288MBIT 400MHZ 144FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
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