參數(shù)資料
型號(hào): MT48LC64M4A2
廠商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件頁數(shù): 52/62頁
文件大?。?/td> 1517K
代理商: MT48LC64M4A2
52
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
WRITE – WITHOUT AUTO PRECHARGE
1
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a
manual
PRECHARGE.
2. 14ns to 15ns is required between <D
IN
m+3
> and the PRECHARGE command, regardless of frequency.
3. x16: A9, A11, and A12 =
Don
t Care
x8: A11 and A12 =
Don
t Care
x4: A12 =
Don
t Care
*CAS latency indicated in parentheses.
-7E
-75
SYMBOL*
t
CMS
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
WR
MIN
1.5
0.8
1.5
37
60
15
15
14
MAX
MIN
1.5
0.8
1.5
44
66
20
20
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
t
CKS
t
CMH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
DISABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRC
tRCD
DQM/
DQML, DQMU
CKE
CLK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
BANK
BANK
ROW
BANK
t
DON
T CARE
D
IN
m
tDH
tDS
D
IN
m
+ 1
D
IN
m
+ 2
D
IN
m
+ 3
COMMAND
tCMH
tCMS
NOP
NOP
NOP
ACTIVE
NOP
WRITE
PRECHARGE
tAH
tAS
tAH
tAS
tDH
tDS
tDH
tDS
tDH
tDS
SINGLE BANK
tCKH
tCKS
COLUMN
m
3
2
T0
T1
T2
T4
T3
T5
T6
T7
T8
T9
ROW
BANK
ROW
ACTIVE
NOP
WR
NOP
ALL BANKs
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