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參數(shù)資料
| 型號(hào)： | MT48LC64M4A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 25/62頁 |
| 文件大?。?/td> | 1517K |
| 代理商： | MT48LC64M4A2 |
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25
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in ele-
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to the start address
and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
Figure 15
WRITE to WRITE
ample is shown in Figure 15. Data
n
+ 1 is either the last
of a burst of two or the last desired of a longer burst. The
256Mb SDRAM uses a pipelined architecture and there-
fore does not require the 2
n
rule associated with a
prefetch architecture. A WRITE command can be initi-
ated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be per-
formed to a different bank.
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
NOP
WRITE
D
IN
n
+ 1
NOP
BANK,
COL
n
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
WRITE
BANK,
COL
n
BANK,
COL
b
D
IN
n
D
IN
n
+ 1
D
IN
b
NOTE:
DQM is LOW. Each WRITE command
may be to any bank.
Figure 13
WRITE Command
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
A10
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A0-A9, A11: x4
A0-A9: x8
A0-A8: x16
A12: x4
A11, A12: x8
A9, A11, A12: x16
BA0,1
ABANK
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| MT48LC64M4A2_03 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM |
| MT48LC64M4A2_99 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Synchronous DRAM 256Mb: x4, x8, x16 SDRAM |
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