參數(shù)資料
型號(hào)： MSC8101M1250F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 378K
代理商： MSC8101M1250F
Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5
4
Freescale Semiconductor
QSIU1
Incorrect clock Synchronization in 1:4 and 1:6 Modes
Date Added:
5/30/2000:
Description:
In PLL enabled mode, the core clock is not synchronized correctly with the bus
clock for even clock ratios, such as 1:4 and 1:6 (bus clock: core clock).
Do not use even bus clock to core clock ratios.
System Number:
5744
Fix Plan:
Rev 0.1
0K40A
QSIU3
TEA May Hang PPC Bus
Date Added:
5/30/2000:
Description:
TEA may hang the PPC bus if it is asserted between specific address and data phas-
es during a split transaction.
Workaround:
Enable Bus Monitor.
System Number:
5724
Fix Plan:
TBD
0K40A
QSIU4
Extended Mode on the Local Bus
Date Added:
6/13/2000:
Description:
Using Extended mode on the local bus can generate incorrect transactions in certain
combinations of consecutive reads and writes.
Workaround:
Do not use Extended mode on the local bus.
System Number:
5959
Fix Plan:
Not currently scheduled
0K40A
QSIU5
Incorrect Data on PowerPC Bus
Date Added:
6/13/2000, modified 10/15/2002
Description:
The following sequence on the PowerPC bus can result in incorrect data:
1.
Read transaction with DACK before AACK.
2.
Failed atomic write transaction
3.
Write transaction
Workaround:
None
System Number:
5823
Fix Plan:
RevA
0K40A
QSIU6
EE[4–5] Pins are Sampled on HRESET,SRESET and PORESET
Date Added:
8/31/2000
Description:
The EE[4–5] pins should be sampled only on PORESET, but they are sampled on
SRESET and HRESET as well. Changing the value of the EE[4–5] pins after PORESET negation
might prevent the chip from booting, because their value might choose a different or undefined
boot configuration.
Workaround:
The EE[4–5] values should be kept constant and equal to the values on PORE-
SET.
Fix Plan:
Rev A
0K40A
QSIU7
Pin IRQ7_INTOUT Not Open Drain
Date Added:
9/6/2000
Description:
INOUT pin IRQ7_INTOUT should be open-drain but not implemented as one.
Workaround:
Buffer INTOUT on the board when it is wire ORed.
Fix Plan:
Rev. A
0K40A
Table 2.
Silicon Errata (Continued)
Errata
Number
Errata Description
Applies
to Mask
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MSC8101VT1250F 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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