參數(shù)資料
型號(hào): MSC8101M1250F
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: Network Digital Signal Processor
中文描述: 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù): 17/28頁
文件大?。?/td> 378K
代理商: MSC8101M1250F
Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5
Freescale Semiconductor
17
CPM44
Zero Insertion Error on MCC
Date Added:
5/30/2000
Description:
When the MCC transmitter is used in HDLC super channel mode, a zero insertion
at the last bit before the flag fails to occur.
Workaround:
There is a microcode patch which fixes the problem.
System Number:
4941
Fix Plan:
Rev A
0K40A
CPM45
Error in CLAV Sample Point
Date Added:
5/30/2000
Description:
In FCC ATM transmit master mode (multiple PHY only), the CLAV signal is sam-
pled 5 clocks before the end of the cell instead of 4 clocks. This is relevant only for back-to-back
transmission sequence.
Workaround:
In multiple PHY fix priority polling mode, by adding a dummy PHY, it is possible
to ensure that the dummy PHY is polled at payload 44 (5 clocks before the end of the cell). This
is possible since the cell length is constant and the number of PHY to poll is also constant.
System Number:
5031
Fix Plan:
Rev A
0K40A
CPM46
Error in Internal Prioritization of CPM Resource
Date Added:
5/30/2000
Description:
Each of the communication controllers (FCC, MCC, SCC, ...) issues request for
service to the CPM with different priorities in order to receive the necessary assistance in time.
Because of an internal connection error, the FCC3 request for service is issued with a much lower
priority than intended. Because of this, FCC3 may sporadically overrun when the CPM is heavily
loaded.
Workaround:
None
System Number:
5663
Fix Plan:
Rev A
0K40A
CPM48
Error in TDM
Date Added:
5/30/2000
Description:
Disabling TDMx may interfere with the operation of TDMy if TDMy uses the SI-
RAM blocks directly above those used by TDMx. For example:
start address of TDMc = 0
start address of TDMb = 2
start address of TDMd = 4
when disabling TDMd, TDMb is affected.
when disabling TDMb, TDMc is affected.
when disabling TDMc, No TDM is affected.
Workaround:
Instead of disabling a TDM, the user can switch to a shadow RAM that contains
only non supported slots in its entries.
System Number:
5714
Fix Plan:
Rev A
0K40A
Table 2.
Silicon Errata (Continued)
Errata
Number
Errata Description
Applies
to Mask
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