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參數(shù)資料
| 型號(hào)： | MSC7119VM1200 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| 中文描述： | 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC |
| 文件頁數(shù)： | 52/56頁 |
| 文件大?。?/td> | 716K |
| 代理商： | MSC7119VM1200 |
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MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Ordering Information
Freescale Semiconductor
52
3.6
Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7119
device. Following are guidelines for signal groups and configuration settings:
Clock and reset signals
.
—
SWTE
is used to configure the MSC7119 device and is sampled on the deassertion of
PORESET
, so it should be
tied to
V
DDC
or
GND
either directly or through pull-up or pull-down resistors until
PORESET
is deasserted. After
PORESET
, this signal can be left floating.
—
BM[0–1]
configure the MSC7119 device and are sampled until
PORESET
is deasserted, so they should be tied to
V
DDIO
or
GND
either directly or through pull-up or pull-down resistors.
—
HRESET
should be pulled up.
Interrupt signals
. When used,
IRQ
pins must be pulled up.
HDI16 signals
.
— When they are configured for open-drain, the
HREQ/HREQ
or
HTRQ/HTRQ
signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the
HRESET
signal as the enable.
— When the device boots through the HDI16, the
HDDS, HDSP
and
H8BIT
pins should be pulled up or down,
depending on the required boot mode settings.
Ethernet MAC/TDM2 signals
. The
MDIO
signal requires an external pull-up resistor.
I
2
C signals
. The
SCL
and
SDA
signals, when programmed for I
2
C, requires an external pull-up resistor.
General-purpose I/O (GPIO) signals
. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
Other signals.
— The
TEST0
pin must be connected to ground.
— The
TPSEL
pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect
DBREQ
to
DONE
(as you would for the MSC8101 device). Connect
DONE
to one of the EVNT
pins, and
DBREQ
to
HRRQ
.
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part
Supply Voltage
Package Type
Pin
Count
Core
Frequency
(MHz)
Solder Spheres
Order Number
MSC7119
1.2 V core
2.5 V memory
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
300
Lead-free
MSC7119VM1200
Lead-bearing
MSC7119VF1200
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC80185 | RF & MICROWAVE TRANSISTORS GENERAL PURPOSE LINEAR APPLICATIONS |
| MSC80186 | GENERAL PURPOSE LINEAR APPLICATIONS RF & MICROWAVE TRANSISTORS |
| MSC80195 | RF & MICROWAVE TRANSISTORS GENERAL PURPOSE LINEAR APPLICATIONS |
| MSC8101 | Silicon Errata for the MSC8101 Processor, Mask 0K40A |
| MSC8101M1375F | Network Digital Signal Processor |
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