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| 型號： | MSC7119VM1200 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| 中文描述： | 低成本16位數(shù)字信號處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC |
| 文件頁數(shù)： | 50/56頁 |
| 文件大小： | 716K |
| 代理商： | MSC7119VM1200 |
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MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Hardware Design Considerations
Freescale Semiconductor
50
3.5.1
V
REF
and V
TT
Design Constraints
V
TT
and V
REF
are isolated power supplies at the same voltage, with V
TT
as a high current power source. This section outlines
the voltage supply design needs and goals:
Minimize the noise on both rails.
V
TT
must track variation in the V
REF
DC offsets. Although they are isolated supplies, one possible solution is to use a
single IC to generate both signals.
Both references should have minimal drift over temperature and source supply.
It is important to minimize the noise from coupling onto V
REF
as follows:
— Isolate V
REF
and shield it with a ground trace.
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than
3 nH.
Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the V
TT
island and ensure a good, solid connection.
Place the V
TT
regulator as closely as possible to the termination island.
— Reduce inductance and return path.
— Tie current sense pin at the midpoint of the island.
3.5.2
Decoupling
The DDR decoupling considerations are as follows:
DDR memory requires significantly more burst current than previous SDRAMs.
In the worst case, up to 64 drivers may be switching states.
Pay special attention and decouple discrete ICs per manufacturer guidelines.
Leverage V
TT
island topology to minimize the number of capacitors required to supply the burst current needs of the
termination rail.
See the Micron DesignLine publication entitled
Decoupling Capacitor Calculation for a DDR Memory Channel
(
http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf
).
Figure 33. SSTL Power Value
Driver
Receiver
V
REF
V
DDQ
V
SS
V
TT
RS
RT
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