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參數(shù)資料
| 型號(hào)： | MSC7119VM1200 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| 中文描述： | 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC |
| 文件頁(yè)數(shù)： | 19/56頁(yè) |
| 文件大?。?/td> | 716K |
| 代理商： | MSC7119VM1200 |
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Electrical Characteristics
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Freescale Semiconductor
19
2.3
Table 4
describes thermal characteristics of the MSC7119 for the MAP-BGA package.
Thermal Characteristics
Section 3.1
,
Thermal Design Considerations
explains these characteristics in detail.
2.4
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC7119.
Note:
The leakage current is measured for nominal voltage values must vary in the same direction (for example, both
V
DDIO
and
V
DDC
vary by +2 percent or both vary by –2 percent).
Table 5. DC Electrical Characteristics
Table 4. Thermal Characteristics for MAP-BGA Package
Characteristic
Symbol
MAP-BGA 17
×
17 mm
5
Unit
Natural
Convection
200 ft/min
(1 m/s) airflow
Junction-to-ambient
1, 2
R
θ
JA
39
31
°C/W
Junction-to-ambient, four-layer board
1, 3
R
θ
JA
23
20
°C/W
Junction-to-board
4
R
θ
JB
12
°C/W
Junction-to-case
5
R
θ
JC
7
°C/W
Junction-to-package-top
6
Ψ
JT
2
°C/W
Notes:
1.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
2.
3.
4.
5.
6.
Characteristic
Symbol
Min
Typical
Max
Unit
Core and PLL voltage
V
DDC
V
DDPLL
1.14
1.2
1.26
V
DRAM interface I/O voltage
1
V
DDM
2.375
2.5
2.625
V
I/O voltage
V
DDIO
3.135
3.3
3.465
V
DRAM interface I/O reference voltage
2
V
REF
0.49
×
V
DDM
1.25
0.51
×
V
DDM
V
DRAM interface I/O termination voltage
3
VTT
V
REF
– 0.04
V
REF
V
REF
+ 0.04
V
Input high CLKIN voltage
V
IHCLK
2.4
3.0
3.465
V
DRAM interface input high I/O voltage
V
IHM
V
REF
+ 0.28
V
DDM
V
DDM
+ 0.3
V
DRAM interface input low I/O voltage
V
ILM
–0.3
GND
V
REF
– 0.18
V
Input leakage current, V
IN
= V
DDIO
I
IN
–1.0
0.09
1
μA
V
REF
input leakage current
I
VREF
—
—
5
μA
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