參數(shù)資料
型號(hào)： MSC7119VM1200
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述： 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁(yè)數(shù)： 23/56頁(yè)
文件大?。?/td> 716K
代理商： MSC7119VM1200
Electrical Characteristics
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Freescale Semiconductor
23
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the divided input clock frequency as shown in
Table 10
.
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown
in
Table 11
.
This bit along with the CKSEL determines the frequency range of the core clock.
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system.
Table 13
summarizes this
restriction.
Table 10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value
Maximum PLLMLTF Value
266
≤
[Divided Input Clock
×
(PLLMLTF + 1)]
≤
532 MHz
266/Divided Input Clock
532/Divided Input Clock
Note:
This table results from the allowed range for F
Loop
. The minimum and maximum multiplication factors are dependent on the
frequency of the Divided Input Clock.
Table 11. F
vco
Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of F
vco
1
266
≤
F
vco
≤
532 MHz
0
133
≤
F
vco
≤
266 MHz
Note:
This table results from the allowed range for F
vco
, which is F
Loop
modified by CLKCTRL[RNG].
Table 12. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Resulting
Division
Factor
Allowed Range
of Core Clock
Comments
11
1
1
266
≤
core clock
≤
300 MHz
Limited by maximum core
frequency
11
0
2
133
≤
core clock
≤
266 MHz
Limited by range of PLL
01
1
2
133
≤
core clock
≤
266 MHz
Limited by range of PLL
01
0
4
66.5
≤
core clock
≤
133 MHz
Limited by range of PLL
Note:
This table results from the allowed range for F
OUT
, which depends on clock selected via CLKCTRL[CKSEL].
Table 13. Core Clock Ranges When Using DDR
DDR Type
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
Comments
DDR 200 (PC-1600)
83–100 MHz
166
≤
core clock
≤
200 MHz
166
≤
core clock
≤
266 MHz
166
≤
core clock
≤
300 MHz
Core limited to 2
×
maximum DDR frequency
Core limited to 2
×
maximum DDR frequency
Core limited to 2
×
maximum DDR frequency
DDR 266 (PC-2100)
83–133 MHz
DDR 333 (PC-2600)
83–150 MHz
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